Did You Know...
...that two musicians were responsible for the invention of color print film? Fascinated by photography, Leopold Godowsky and Leopold Mannes worked together to produce an easy-to-use, practical color film. They worked full time as music teachers and gave concerts while experimenting during their off hours in Mannes' kitchen. Their success earned them full-time, well-paying jobs at Kodak and their efforts resulted in Kodachrome film, which was introduced in 1935.
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| Application No. | Application Title | Issue Date |
| 20120106611 | PHASE LOCKING LOOP A phase-locking loop (PLL) for use with orthogonal frequency division multiplexed signals. In one embodiment, a wireless receiver includes a PLL is configured to reduce phase and frequency divergence between the wireless receiver and a transmitter of a packet received b... | 05/03/2012 |
| 20120081693 | SYSTEM FOR DEMODULATING A SIGNAL A demodulating system (100) for demodulating a phase-modulated input signal (Si) comprises:
| 04/05/2012 |
| 20110280344 | DYNAMIC BANDWIDTH CONTROL SCHEME OF A FRAC-N PLL IN A RECEIVER A receiver, in accordance with one embodiment of the present invention, includes a mixer, a filter, a received signal strength indicator, and a control loop. The mixer is adapted to convert the frequency of a received signal. The filter is adapted to filter out undesire... | 11/17/2011 |
| 20110116578 | Mobile Communication System with Integrated GPS Receiver A receiver includes a mixer, a poly phase filter, a channel select filter, an analog-to-digital converter and a HI/LO side reject selection unit. The mixer downconverts a signal to generate an in-phase signal and a quadrature signal. The poly phase filter for generates ... | 05/19/2011 |
| 20100278285 | WIRELESS SIGNAL RECEIVING METHOD AND RECEIVER UTILIZING THE SAME A receiver receiving a Radio Frequency (RF) signal and generating a baseband signal is provided. An RF module receives the RF signal and down convert the RF signal according to a first oscillation frequency to generate an Intermediate Frequency (IF) signal. An IF module... | 11/04/2010 |
| 20100232548 | DEMODULATION AND DECODING FOR FREQUENCY MODULATION (FM) RECEIVERS WITH RADIO DATA SYSTEM (RDS) OR RADIO BROADCAST DATA SYSTEM (RBDS) Demodulation and decoding for frequency modulation (FM) receivers with radio data system (RDS) or radio broadcast data system (RBDS). An example of a method for processing a signal in a receiver includes quantizing a demodulated signal to generate bits in response to re... | 09/16/2010 |
| 20100142652 | DEMODULATOR WITH SIGNAL PRECONDITIONER A method and apparatus for demodulating an input signal, for example, in a communications system, is disclosed. The apparatus includes a signal preconditioner and a demodulator. The signal preconditioner may include a low-pass filter and a hysteretic comparator that are... | 06/10/2010 |
| 20090296857 | Frequency lock detection A system and method are provided for detecting the frequency acquisition of a synthesized signal in a non-synchronous communications receiver. The method accepts a non-synchronous communication signal having an input data signaling frequency, and compares the input data... | 12/03/2009 |
| 20090279642 | Calibrated Quadrature Generation for Multi-GHZ Receiver An integrated receiver circuit includes aphase locked loop circuit (21) with a voltage controlled oscillator (VCO) (25) and a quadrature generator circuit (29) which uses hybrid-branch line coupler circuits (27, 28) coupled to buffered VCO ou... | 11/12/2009 |
| 20090245426 | STORING LOG LIKELIHOOD RATIOS IN INTERLEAVED FORM TO REDUCE HARDWARD MEMORY An apparatus and method for storing log likelihood ratios in an interleaved form comprising receiving a plurality of interleaved codewords; obtaining at least one log likelihood ratio (LLR) for the plurality of interleaved codewords; storing the at least one LLR in a me... | 10/01/2009 |
| 20090232250 | COMMUNICATION SYSTEM, RECEIVER AND RECEPTION METHOD A communication system includes: a transmitter adapted to transmit a synchronizing clock and serial data synchronous with the synchronizing clock over a line at low amplitude; and a receiver adapted to receive the serial data and synchronizing clock from the transmitter... | 09/17/2009 |
| 20090207943 | Semiconductor Circuit Device A semiconductor circuit device is provided which can attain more stable operations against noise in a data communication system without increasing the power consumption of an overall system, thereby improving the reliability of data communication. For a demodulation bas... | 08/20/2009 |
| 20090135956 | METHOD AND APPARATUS FOR PRECISE OPEN LOOP TUNING OF REFERENCE FREQUENCY WITHIN A WIRELESS DEVICE A communications subsystem for a wireless device for correcting errors in a reference frequency signal. The communications subsystem comprises a frequency generator for generating the reference frequency signal and a closed loop reference frequency correction module tha... | 05/28/2009 |
| 20090122919 | RECEIVER CIRCUIT, APPLICATION OF A FIRST AND A SECOND PROPORTIONAL ELEMENT OF A DIGITAL PLL STRUCTURE, AND METHOD FOR RECEIVING A FREQUENCY-SHIFT KEYED SIGNAL A receiver circuit, application of a first proportional element and a second proportional element of a digital PLL structure, and method for receiving a frequency-shift keyed signal are provided. A phase signal is calculated from an in-phase signal and a quadrature sign... | 05/14/2009 |
| 20090074127 | PHASE LOCKING METHOD AND APPARATUS A phase locking method and apparatus by which a phase of an input signal is locked using the input signal and a clock signal, where the phase locking method includes generating n multi-phase clock signals using the clock signal where n is an integer, generating n multi-... | 03/19/2009 |
| 20090016466 | Complex digital phase locked loop for use in a demodulator and method of optimal coefficient selection A complex digital phase locked loop for use in a digital demodulator includes a phase detector for producing a phase error indicative of a difference in phase between a complex digital input signal and a complex digital feedback signal. The phase error is input to a con... | 01/15/2009 |
| 20080240296 | Iterative sequential carrier acquisition A system and method for iterative sequential carrier acquisition for estimating and correcting large carrier frequency offsets without adding significantly to receiver complexity or preamble length. A coarse frequency estimation is performed during a brief carrier acqui... | 10/02/2008 |
| 20080240298 | Method and/or apparatus for stabilizing the frequency of digitally synthesized waveforms An apparatus comprising a first circuit, a second circuit, a third circuit and a fourth circuit. The first circuit may be configured to generate a demodulated signal in response to (i) a modulated signal and (ii) a seed value. The second circuit may be configured to gen... | 10/02/2008 |
| 20080159443 | PHASE SYNCHRONOUS DEVICE AND METHOD FOR GENERATING PHASE SYNCHRONOUS SIGNAL Disclosed are a phase synchronous device for improving jitter of an output signal and a method for generating a phase synchronous signal. The phase synchronous device includes a phase detector detecting a phase difference between first and second signals to output a pha... | 07/03/2008 |
| 20080137714 | Spread Spectrum Signal A spread-spectrum signal comprises a spreading waveform modulating a carrier wave and containing a real linear combination of a first waveform at a first waveform rate and a second waveform at a second waveform rate, the first waveform rate being distinct from the secon... | 06/12/2008 |
| 20080107154 | PHASE MODULATION METHOD FOR SPREAD SPECTRUM CLOCK GENERATOR Spread spectrum clock generation (SSCG) using phase modulation. A first clock signal having a first frequency spectrum may be modulated using phase modulation to produce a second clock signal. The phase modulation may include providing a phase modulation profile corresp... | 05/08/2008 |
| 20080089445 | Mobile Communication System with Integrated GPS Receiver A Global Positioning System (GPS) receiver integrated with a cellular phone system, comprising a single-balanced mixer, a poly phase filter, a channel select filter, an analog-to-digital converter, a reference frequency source, and a PLL unit is disclosed. The single-ba... | 04/17/2008 |
| 20070189360 | Method and apparatus for generation of asynchronous clock for spread spectrum transmission A circuit for spread spectrum rate control uses a first interpolator to phase interpolate between a first signal and a second signal and generate a first output signal based on a first control signal. A second interpolator is utilized to phase interpolate between a thir... | 08/16/2007 |
| 20070127600 | Timing recovery circuit A timing recovery circuit capable of enhancing the reliability of timing recovery in a receiver apparatus in a communication system that employs the scheme of modulating the amplitude of a carrier wave. In the receiver apparatus which receives a transmitted signal creat... | 06/07/2007 |
| 20070104292 | Timing recovery phase locked loop Methods and apparatus for timing recovery phase locked loops. One embodiment provides a phase detectors for generating phase difference signals on the basis of a received feedback signal and an input clock signal and an input data signal, respectively. A digital control... | 05/10/2007 |
| 20070098114 | Detection of large carrier offsets using a timing loop A method and apparatus for the detection and correction of large carrier offsets. A set of known correction carrier offsets are used to translate an input signal having a carrier offset. After applying each correction carrier offset, a state of a timing recovery loop is... | 05/03/2007 |
| 20070092040 | Synchronizing apparatus, synchronizing method, synchronizing program and data reproduction apparatus A synchronizing apparatus, which controls, by a PLL circuit, a sampling clock to be used to sample input data and synchronizes a phase of the sampling clock with a target phase that is desirable for sampling the input data, includes: phase error detection means for dete... | 04/26/2007 |
| 20070092039 | MULTI-CHANNEL SERDES RECEIVER FOR CHIP-TO-CHIP AND BACKPLANE INTERCONNECTS AND METHOD OF OPERATION THEREOF A multi-channel serializing/deserializing (“serdes”) receiver, a method of operating the receiver and an integrated circuit configured as a serdes receiver. In one embodiment, the receiver includes:(1) a central frequency synthesizer configured to provide both in-ph... | 04/26/2007 |
| 20070081613 | Ultra wideband networks system and method capable of switching to high-speed mode or low-speed mode An ultra wideband network transmitter and receiver, and a method capable of switching to a high-speed mode or a low-speed mode are provided. The transmitter includes a multi-band orthogonal frequency division multiplexing (MB-OFDM) modem; a direct sequence code division... | 04/12/2007 |
| 20070076822 | Method and system for estimating frequency offsets A method is provided for estimating a frequency offset value. This method includes: receiving a signal from the transmitting device at the receiving device, the received signal having a transmitter frequency (510); generating a local signal at the receiving devic... | 04/05/2007 |
| 20070064836 | Format efficient timing acquisition for magnetic recording read channels A timing recovery circuit for magnetic recording applications that use preamble synchronization bits. The timing recovery circuit uses a modified digital phase lock loop having a digital rotator. An analog to digital converter (ADC) receives an analog input and provides... | 03/22/2007 |
| 20070064837 | Circuits and methods for acquiring a frequency of a data bitstream Circuits and methods for recovering a periodic signal from a data signal. One circuit generally includes (1) a recovery circuit configured to produce a reference signal from the data signal, (2) a frequency detector circuit configured to produce a detector output in res... | 03/22/2007 |
| 20070019760 | System and method for operating a phase-locked loop A mobile communications system comprising a phase-locked loop (PLL), radio frequency (RF) circuitry, and control circuitry configured to activate the PLL and the RF circuitry during a plurality of substantially mutually exclusive time intervals is provided. ... | 01/25/2007 |
| 20060280240 | Information read device and read signal processing circuit An optical disk read signal processing system for Blu-ray disc systems to ensure stable phase-locked locked operation even with a low signal-to-noise ratio. This system changes a loop configuration of a phase lock loop circuit according to the operating state, and utili... | 12/14/2006 |
| 20060269014 | Oscillator frequency selection According to some embodiments, a frequency adjuster adjusts a frequency of an oscillator. For example, the frequency adjuster might include a plurality of capacitors that are selectable using a digital control signal, and selection logic may adjust the digital control s... | 11/30/2006 |
| 20060239384 | Wideband phase shift device The invention relates to a wideband phase shift device. A phase shift φ is introduced on the fixed frequency local oscillator. The principle of the invention is to realise a double translation of the input signals. The phase variation introduced at the level of the loc... | 10/26/2006 |
| 20060209990 | Communication semiconductor integrated circuit device incorporating a PLL circuit therein A communication semiconductor high-frequency IC device includes an offset-PLL transmission circuit. The device does not require an intermediate-frequency voltage controlled oscillator (IFVCO) to generate an intermediate-frequency (IF) signal and can modulate and demodul... | 09/21/2006 |
| 20060146959 | Look-ahead digital loop filter for clock and data recovery The present invention enhances the performance of a clock and data recovery (CDR) circuit by employing look-ahead techniques to produce a low latency timing adjustment. In one example of the invention employed in a CDR circuit having a decimation filter processing the C... | 07/06/2006 |
| 20060115019 | Complex digital phase locked loop for use in a demodulator and method of optimal coefficient selection A complex digital phase locked loop for use in a digital demodulator includes a phase detector for producing a phase error indicative of a difference in phase between a complex digital input signal and a complex digital feedback signal. The phase error is input to a con... | 06/01/2006 |
| 20060115020 | Clock data recovery circuit with phase decision circuit A clock data recovery circuit with feedback type phase discrimination. The clock data recovery circuit has an output signal of B bits and comprises a sampler, a phase region decision circuit, a phase status register and a multiplexer. The sampler oversamples k*B bits pe... | 06/01/2006 |
