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| Application No. | Application Title | Issue Date |
| 20120127774 | SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE All interface pins for transmitting and receiving a signal having a predetermined function of a semiconductor integrated circuit element are formed on an outer periphery of the semiconductor integrated circuit element along one side of the semiconductor integrated circu... | 05/24/2012 |
| 20120106227 | INTEGRATED CIRCUIT An integrated circuit includes a normal data storage unit configured to store normal data and output the stored normal data in response to a write command, a read command, and an address signal in a normal operation mode, a test data storage unit configured to store the... | 05/03/2012 |
| 20120106228 | METHOD AND APPARATUS FOR OPTIMIZING DRIVER LOAD IN A MEMORY PACKAGE An apparatus is provided that includes a plurality of array dies and at least two die interconnects. The first die interconnect is in electrical communication with a data port of a first array die and a data port of a second array die and not in electrical communication... | 05/03/2012 |
| 20120106230 | SEMICONDUCTOR MEMORY DEVICE The memory cell array has memory cells each positioned at respective intersections between a plurality of first wirings and a plurality of second wirings. Each of the memory cells has a rectifier element and a variable resistance element connected in series. The resista... | 05/03/2012 |
| 20120106229 | Semiconductor device To include stacked plural core chips, each of which includes a first through silicon via for transferring write data and a second through silicon via for transferring read data, and an interface chip commonly connected to the core chips. The interface chip includes a da... | 05/03/2012 |
| 20120106253 | THREE-DIMENSIONAL MEMORY DEVICE INCORPORATING SEGMENTED ARRAY LINE MEMORY ARRAY A three-dimensional (3D) high density memory array includes multiple layers of segmented bit lines (i.e., sense lines) with segment switch devices within the memory array that connect the segments to global bit lines. The segment switch devices reside on one or more lay... | 05/03/2012 |
| 20120081941 | SEMICONDUCTOR MEMORY DEVICE HAVING AN ELECTRICALLY FLOATING BODY TRANSISTOR A semiconductor memory cell is formed in a semiconductor. The semiconductor memory cell includes: a floating body region defining at least a portion of a surface of the semiconductor memory cell, the floating body region having a first conductivity type; and a buried re... | 04/05/2012 |
| 20120054562 | SEMICONDUCTOR MEMORY DEVICE A semiconductor memory device having a bank including a redundancy cell block and a plurality of normal cell blocks includes a plurality of normal data inputting/outputting units configured to respectively input/output data from the normal cell blocks in response to a f... | 03/01/2012 |
| 20120044734 | BIT LINE SENSE AMPLIFIER LAYOUT ARRAY, LAYOUT METHOD, AND APPARATUS HAVING THE SAME A bit line sense amplifier layout array includes N sense amplifier layout regions, which are arranged adjacent each other and have a sense amplifier, respectively. (N+1−i) bit lines and i complementary bit lines are arranged in an ith sense amplifier layout... | 02/23/2012 |
| 20120044735 | STRUCTURES WITH INCREASED PHOTO-ALIGNMENT MARGINS Methods and structures are provided for increasing alignment margins when contacting pitch multiplied interconnect lines with other conductive features in memory devices. The portions of the lines at the periphery of the memory device are formed at an angle and are wide... | 02/23/2012 |
| 20120039104 | METHOD AND APPARATUS FOR BURIED WORD LINE FORMATION An integrated circuit with a memory cell is disclosed. The integrated circuit with a memory cell includes: a word line disposed in a word line trench of a substrate; a bit line disposed below the word line in a bit line trench and extending orthogonal to the word line; ... | 02/16/2012 |
| 20120033477 | MEMORY MODULES HAVING DAISY CHAIN WIRING CONFIGURATIONS AND FILTERS Examples described include memory units coupled to a controller using a daisy chain wiring configuration. A filter located between a first memory unit and the controller attenuates a particular frequency, which may improve ringback in a signal received at the memory uni... | 02/09/2012 |
| 20120026773 | SEMICONDUCTOR MEMORY APPARATUS HAVING SENSE AMPLIFIER Disclosed is a semiconductor memory apparatus comprising an upper mat and a lower mat with a sense amplifier array region in between, where the sense amplifier array region includes a plurality of sense amplifiers. There is also a plurality of bit lines configured to ex... | 02/02/2012 |
| 20120020138 | TRANSISTOR HAVING AN ADJUSTABLE GATE RESISTANCE AND SEMICONDUCTOR DEVICE COMPRISING THE SAME A memory device comprises an array of memory cells each capable of storing multiple bits of data. The memory cells are arranged in memory strings that are connected to a common source line. Each memory cell includes a programmable transistor connected in series with a r... | 01/26/2012 |
| 20120008361 | SEMICONDUCTOR MEMORY DEVICE A semiconductor memory device includes cell gate lines arranged in parallel over a semiconductor substrate, gate lines for select transistors disposed over the semiconductor substrate adjacent to the gate lines of the outermost memory cells, from among the gate lines fo... | 01/12/2012 |
| 20120002456 | METHOD OF ARRANGING PADS IN SEMICONDUCTOR DEVICE, SEMICONDUCTOR MEMORY DEVICE USING THE METHOD, AND PROCESSING SYSTEM HAVING MOUNTED THEREIN THE SEMICONDUCTOR MEMORY DEVICE A method of arranging pads in a semiconductor memory device, the semiconductor memory device using the method, and a processing system having mounted therein the semiconductor memory device. The method includes classifying pads provided in a memory chip of the semicondu... | 01/05/2012 |
| 20110318964 | CARD DESIGN WITH FULLY BUFFERED MEMORY MODULES AND THE USE OF A CHIP BETWEEN TWO CONSECUTIVE MODULES An AMB component and a connection interface for a memory installation with fully buffered Dimm memory modules connected in series. The AMB component is disposed on a connecting line from memory modules to a memory controller of the memory installation to re-amplify the ... | 12/29/2011 |
| 20110317465 | Methods and Systems for Reducing Heat Flux in Memory Systems The memory module includes front and back faces. Multiple devices are disposed on each of the faces. A first control line serially connects a first group of devices on both the front and back faces so that the first group of devices commonly contribute multiple bits to ... | 12/29/2011 |
| 20110305058 | NONVOLATILE MEMORY DEVICE AND METHOD OF FABRICATING SAME A nonvolatile memory device includes multiple variable resistive elements formed on a substrate; multiple bit lines formed on the variable resistive elements, extended in a first direction, and separated from each other by a first pitch; multiple circuit word lines form... | 12/15/2011 |
| 20110305059 | Semiconductor Memory Devices Semiconductor memory devices include a first storage layer and a second storage layer, each of which includes at least one array, and a control layer for controlling access to the first storage layer and the second storage layer so as to write data to or read data from ... | 12/15/2011 |
| 20110305060 | WIRING SUBSTRATE IN WHICH EQUAL-LENGTH WIRES ARE FORMED In a wiring substrate, a double data rate (DDR) memory and a memory controller controlling the DDR memory are mounted. Further, in the wiring substrate, plural equal-length wires connecting the DDR memory and the memory controller are formed. The plural equal-length wir... | 12/15/2011 |
| 20110292708 | 3D SEMICONDUCTOR DEVICE A three-dimensional (3D) semiconductor device may include a stack of chips, including a master chip and one or more slave chips. I/O connections of slave chips need not be connected to channels on a motherboard, and only electrode pads of a master chip may be connected ... | 12/01/2011 |
| 20110267866 | EXTENSIBLE THREE DIMENSIONAL CIRCUIT HAVING PARALLEL ARRAY CHANNELS An extensible three dimensional circuit having parallel array channels includes an access layer and crossbar array layers overlying the access layer and being electrically connected to the access layer. The crossbar array layers include parallel channels, the parallel c... | 11/03/2011 |
| 20110267867 | SEMICONDUCTOR DEVICE A semiconductor device includes a memory cell array area, a peripheral circuit area on a periphery of the memory cell array area, and a boundary area having a specific width between the memory cell array area and the peripheral circuit area, the memory cell array area i... | 11/03/2011 |
| 20110261603 | INTEGRATED CIRCUIT PACKAGE WITH MULTIPLE DIES AND BUNDLING OF CONTROL SIGNALS A package includes a first die and a second die, at least one of said first and second dies being a memory. The dies are connected to each other through an interface. The interface is configured to transport a plurality of control signals. The number of control signals ... | 10/27/2011 |
| 20110255324 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE CAPABLE OF SECURING GATE PERFORMANCE AND CHANNEL LENGTH A semiconductor integrated circuit device includes a semiconductor substrate; a plurality of word lines extending parallel to one another on the semiconductor substrate; a plurality of bit lines extending parallel to one another on the semiconductor substrate, arranged ... | 10/20/2011 |
| 20110255323 | MEMORY/LOGIC CONJUGATE SYSTEM There is a problem that a bandwidth bottleneck occurs because a crossbar switch is used to cope with an increase in scale. In an example of a memory/logic conjugate system according to the present invention, a plurality of cluster memory chips each including a plurality... | 10/20/2011 |
| 20110249483 | STACKED MEMORY DEVICE HAVING INTER-CHIP CONNECTION UNIT, MEMORY SYSTEM INCLUDING THE SAME, AND METHOD OF COMPENSATING FOR DELAY TIME OF TRANSMISSION LINE A stacked semiconductor memory device is provided which includes a first memory chip including a first transmission line, a second transmission line, and a logic circuit configured to execute a logic operation on a first signal of the first transmission line and a secon... | 10/13/2011 |
| 20110249482 | SEMICONDUCTOR MEMORY DEVICE According to one embodiment, a semiconductor memory device includes a first active area in a semiconductor substrate, memory cells on the semiconductor substrate, first bit lines, first line, a second line, a third line, and a fourth line. The first line extends in a di... | 10/13/2011 |
| 20110242870 | STACKED MEMORY AND DEVICES INCLUDING THE SAME In one embodiment, the stacked memory includes a first group of stacked memory chips, a second group of stacked memory chips, and connection terminals configured to electrically connect a first memory chip among the stacked memory chips in the first group to a second me... | 10/06/2011 |
| 20110228583 | SEMICONDUCTOR MEMORY DEVICE According to one embodiment, a semiconductor memory device includes a memory cell array, a first sense amplifier circuit, and a second sense amplifier circuit. The memory cell array includes a plurality of first memory cell units, a plurality of second memory cell units... | 09/22/2011 |
| 20110205777 | Semiconductor memory device having vertical transistors A device includes a first region including a plurality of first memory elements and a plurality of first vertical transistors, the first vertical transistors comprising a plurality of first selective transistors and a first switching transistor, each of the first select... | 08/25/2011 |
| 20110199808 | MEMORY DEVICE FROM WHICH DUMMY EDGE MEMORY BLOCK IS REMOVED A semiconductor memory device having an open bitline memory structure from which an edge dummy memory block is removed, the semiconductor memory device includes a memory block, an edge sense amplification block including a first sense amplifier having a first bitline, a... | 08/18/2011 |
| 20110199805 | Selective access memory circuit A selective access memory circuit (SAMC) is described. The SAMC is a class of complex programmable memory device (CPMD) that reconfigures access to memory cells by using gates in an integrated gate array mechanism configured at regular intervals in memory arrays. CPMDs ... | 08/18/2011 |
| 20110199806 | UNIVERSAL STRUCTURE FOR MEMORY CELL CHARACTERIZATION An integrated circuit includes a structure, where the structure includes a memory base cell, a first port set, a second port set, and a set of other ports, where the memory base cell includes a first storage node set, a second storage node set, and a set of other nodes,... | 08/18/2011 |
| 20110194326 | MEMORY DIES, STACKED MEMORIES, MEMORY DEVICES AND METHODS Memory die, stacks of memory dies, memory devices and methods, such as those to construct and operate such die, stacks and/or memory devices are provided. One such memory die includes an identification configured to be selectively coupled to an external select connectio... | 08/11/2011 |
| 20110188286 | ELECTROMECHANICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME In a memory device and a method of forming the same, in one embodiment, the memory device comprises a first word line structure on a substrate, the first word line structure extending in a first direction. A bit line is provided over the first word line structure and sp... | 08/04/2011 |
| 20110188285 | PERMANENT SOLID STATE MEMORY A permanent solid state memory device is disclosed. Recording data in the permanent solid state memory device forms voids in a data layer between a first wire array and a second wire array. Wires of the first wire array extend transversely to wires in the second wire ar... | 08/04/2011 |
| 20110182098 | INTEGRATED CIRCUITS AND METHODS FOR FORMING THE SAME An integrated circuit including a first memory array and a logic circuit coupled with the first memory array. All active transistors of all memory cells of the first memory array and all active transistors of the logic circuit are Fin field effect transistors (FinFETs) ... | 07/28/2011 |
| 20110179210 | Semiconductor device and data processing system A semiconductor device includes: first transmission wirings each transmitting a small-amplitude signal between one of a plurality of first drivers and one of a plurality of receivers; a second transmission wiring transmitting a reference signal connected to each of the ... | 07/21/2011 |
