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| Application No. | Application Title | Issue Date |
| 20070297207 | Methods and apparatus for content addressable memory arrays including shared match lines Embodiments of the present invention provide content addressable memory (CAM) arrays that include shared match lines. Other embodiments may be described and claimed.... | 12/27/2007 |
| 20070291524 | Nanoscale Content-Addressable Memory A combined content addressable memory device and memory interface is provided. The combined device and interface includes one or more one molecular wire crossbar memories having spaced-apart key nanowires, spaced-apart value nanowires adjacent to the key nanowires, and ... | 12/20/2007 |
| 20070258277 | MATCHLINE SENSE CIRCUIT AND METHOD A matchline sense circuit for detecting a rising voltage on a matchline of a CAM array is disclosed. The circuit initially precharges a matchline to ground before turning on a current source to supply current to the matchline and raise the voltage of the matchline. A re... | 11/08/2007 |
| 20070247884 | Attribute cache memory A memory system according to one embodiment includes a plurality of content addressable word decoders, and memory cells associated with each of the word decoders. A memory system according to another embodiment includes a word decoder storing an identifier which is a su... | 10/25/2007 |
| 20070247885 | Content addressable memory An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larg... | 10/25/2007 |
| 20070242493 | MATCH SENSING CIRCUIT FOR A CONTENT ADDRESSABLE MEMORY DEVICE A Content Addressable Memory (CAM) device with an improved match sensing circuit is provided. The CAM is provided with a dummy cell and a respective dummy match line, as well as a reference dummy match line. The dummy match line is designed to be evaluated after all oth... | 10/18/2007 |
| 20070217244 | High performance and scalable width expansion architecture for fully parallel CAMs A technique that provides highly scalable width expansion architecture for cascading CAMs to facilitate searching of increased wordlengths. In one example embodiment, this is achieved by combining a plurality of CAM devices in a serial cascade arrangement. Each CAM devi... | 09/20/2007 |
| 20070206397 | LOW POWER MATCH-LINE SENSING CIRCUIT A low power matchline sensing scheme where power is distributed according to the number of mismatching bits occurring on a matchline is disclosed. In particular, match decisions involving a larger number of mismatched bits consume less power compared to match decisions ... | 09/06/2007 |
| 20070206396 | PHYSICAL PRIORITY ENCODER A priority encoder can be used for a Content-Addressable Memory (CAM) device that typically has an array of CAM cells arranged in columns and rows with each row having a match signal indicative that compare data has matched data within the respective row. A priority enc... | 09/06/2007 |
| 20070195570 | Serial content addressable memory A technique is presented for implementing a content addressable memory (CAM) function using traditional memory, where the input data is serially loaded into a serial CAM. Various additions, which allow for predicting the result of a serial CAM access coincident with the... | 08/23/2007 |
| 20070183191 | Stacked capacitor memory Stacked capacitor memory is realized, wherein a capacitor stores data and a diode serves as an access device instead of MOS transistor, the first terminal is connected to a word line, the second terminal is connected to the first electrode of the capacitor which serves ... | 08/09/2007 |
| 20070183178 | Semiconductor memory device There is provided a control circuit (409) for fetching a result of a comparison of a part of bits of entry data with a corresponding bit of comparison data and prohibiting a comparison of residual bits in the entry data with the corresponding bit of the compariso... | 08/09/2007 |
| 20070165436 | High-speed and low-power differential non-volatile content addressable memory cell and array A differential non-volatile content addressable memory array has a differential non-volatile content addressable memory cell which uses a pair of non-volatile storage elements. Each of the non-volatile storage elements can be a split-gate floating gate transistor or a s... | 07/19/2007 |
| 20070165435 | Low-power CAM In one embodiment, a CAM is provided that includes; a plurality of memory cells grouped to store a word, wherein the memory cells are organized into a plurality of ripple groups, each ripple group including a complex logic gate configured to determine whether a stored c... | 07/19/2007 |
| 20070139991 | Cache hit logic of cache memory and processor chip having the same A processor chip having a cache hit logic for determining whether data required by a processor is stored in a cache memory includes a dummy cell string that operates the same as a sense amplifier for sensing a tag address stored in a tag memory cell array and a comparis... | 06/21/2007 |
| 20070139990 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE A nonvolatile semiconductor memory device has a high read output and is not affected by a noise of adjacent bit lines. The memory device is capable of performing high speed read operations. Each bit of a memory as formed by a plurality of memory cells. The memory cells ... | 06/21/2007 |
| 20070133244 | METHOD AND APPARATUS FOR WIDE WORD DELETION IN CONTENT ADDRESSABLE MEMORIES A system and method for searching and deleting segmented wide word entries in a CAM array is disclosed. A normal CAM search operation is executed to find the first word segment of a wide word. Once found, a search and delete operation is executed to find all successive ... | 06/14/2007 |
| 20070133243 | A content addressable memory including capacitor memory cell A content addressable memory is realized, wherein capacitor stores data and diode controls to store data “1” or “0”, which diode has four terminals, first terminal serves as word line, second terminal serves as storage node, third terminal is floating, and fourt... | 06/14/2007 |
| 20070109829 | Dynamic time sequence control device and its method for word matching circuit A dynamic time sequence control device and its method for a word matching circuit. The word matching circuit includes a first switch connected between an input voltage and a node to respond to a control signal generated by a pre-charging circuit so that within a pre-cha... | 05/17/2007 |
| 20070103953 | CONTENT ADDRESSABLE MEMORIES (CAMs) BASED ON A BINARY CAM AND HAVING AT LEAST THREE STATES Content addressable memories are disclosed that provide at least three states and are based on existing binary CAM devices. A higher order CAM having at least three states comprises a binary CAM having two binary bits; and a logic circuit to configure the two binary bit... | 05/10/2007 |
| 20070097723 | Area efficient stacked TCAM cell for fully parallel search An area efficient stacked TCAM cell for fully parallel search. The TCAM cell includes a top half circuit portion interconnected with a replicated bottom half circuit portion such that there is a shared match line between each of the half circuit portions. Each TCAM cell... | 05/03/2007 |
| 20070097722 | Circuit and method for subdividing a CAMRAM bank by controlling a virtual ground A CAM bank is functionally divided into two or more sub-banks, without replication CAM driver circuits, by disabling all match line discharge circuits in the bank, and selectively enabling the discharge circuits in comprising sub-banks. At least one selectively actuated... | 05/03/2007 |
| 20070086227 | Error protected ternary content-addressable memories and lookup operations performed thereon Ternary content-addressable memory (TCAM) entries are disclosed for use in performing error-protected lookup operations by allowing an error budget of u deviations in values stored in each entry. Each TCAM entry is configured to identify a hit condition (else a miss con... | 04/19/2007 |
| 20070081373 | Cam circuit and output method thereof A CAM circuit according to the present invention used for a cash memory and the like, wherein an address is obtained by designating a data, comprises a data compare unit for comparing a data stored in a memory unit to a data of a compare line in a state where a match li... | 04/12/2007 |
| 20070064461 | LOW POWER CONTENT ADDRESSABLE MEMORY A low power content addressable memory (CAM) device. The CAM device receives an N-bit comparand value and, in response, activates less than N compare lines within the CAM device to compare each of the N bits of the comparand value with contents of CAM cells coupled to t... | 03/22/2007 |
| 20070058407 | Semiconductor memory device A CAM (Content Addressable Memory) cell includes first and second data storage portions storing data, horizontal port write gates for storing data applied through a match line pair in the data storage portions in a data write through a horizontal port, and search/read g... | 03/15/2007 |
| 20070047282 | Method and apparatus for implementing power saving for content addressable memory A method and apparatus are provided for implementing power saving in a content addressable memory (CAM). A compare array is matched against a key and if a match occurs then logic coupled to the compare array generates a hit signal. A data array includes precharge circui... | 03/01/2007 |
| 20070047281 | STORAGE ELEMENT WITH CLEAR OPERATION AND METHOD THEREOF A storage device and a method in the storage element, where the storage element has a first data storage node and a second data storage node and where the first data storage node is coupled to a bit line via a first pass transistor and where the second data storage node... | 03/01/2007 |
| 20070019454 | Glitch protect valid cell and method for maintaining a desired state value A glitch protect valid cell and method for maintaining a desired logic state value in response to a glitch signal and a timing signal. The glitch protect valid cell may be integrated with a content addressable memory (CAM) array for indicating whether word data stored w... | 01/25/2007 |
| 20070019455 | PROGRAMMABLE PRIORITY ENCODER A programmable priority encoder is disclosed for use with the device such as a Content Addressable Memory (CAM) device having a plurality of array objects to be encoded in binary and arranged in row and columns. Match lines are adapted to be connected to a plurality of ... | 01/25/2007 |
| 20070014138 | CONTENT ADDRESSABLE MEMORY STRUCTURE A content addressable memory including a first array of memory cells, and a second array of memory cells. A search logic circuit is configured to prevent a discharge of the second array of memory cells when a search of the first array of memory cells finds certain data.... | 01/18/2007 |
| 20070014137 | Banked cache with multiplexer Systems and methods associated with cache banking are described. One exemplary system embodiment includes an array that is physically banked into multiple banks. While inputs may be provided to the banked array at a first rate, an array access may take more than one cyc... | 01/18/2007 |
| 20070014139 | COMPARE CIRCUIT FOR A CONTENT ADDRESSABLE MEMORY CELL A ternary content addressable memory (CAM) cell is disclosed for providing reduced or minimized matchline (ML) capacitance and for increasing current between matchline and tail-line in the case of a mismatch. The speed of a CAM cell is generally inversely proportional t... | 01/18/2007 |
| 20070014163 | NAND Flash Memory Devices and Methods of LSB/MSB Programming the Same Multiple bits are programmed in a NAND flash memory device by programming a memory cell with an LSB; storing the LSB into a cache register from the memory cell; programming the memory cell with an MSB that is stored in a main register; storing a data bit into the main r... | 01/18/2007 |
| 20070008760 | Highly integrated ternary semiconductor memory device A TCAM (ternary content addressable memory) cell array is provided with a search input node into which one bit of search data is inputted, a plurality of data input nodes into which a bit corresponding to one bit of search data is inputted, and a plurality of memory cel... | 01/11/2007 |
| 20070008759 | METHOD AND APPARATUS FOR INTERCONNECTING CONTENT ADDRESSABLE MEMORY DEVICES A CAM system comprising a plurality of CAM devices connected in a serial cascade arrangement, the CAMs in the cascade being connected to an adjacent CAM by a respective forwarding bus, with at most a first CAM in the cascade being connected to a receive data signals fro... | 01/11/2007 |
| 20060285374 | Content addressable memory cell A content addressable memory cell may include a non-volatile memory storage transistor coupled to an enhancement transistor. In some embodiments, the enhancement transistor may be a select cell. In some embodiments, the storage transistor may use substrate hot electron ... | 12/21/2006 |
| 20060268592 | Low power microprocessor cache memory and method of operation Techniques for processing transmissions in a communications (e.g., CDMA) system including the use of a digital signal processor. The digital signal processor includes a cache memory system and associates a plurality of cache memory match lines with addressable memory li... | 11/30/2006 |
| 20060262583 | RANGE REPRESENTATION IN A CONTENT ADDRESSABLE MEMORY (CAM) USING AN IMPROVED ENCODING SCHEME In a method and apparatus for encoding a bit field within a memory device, the bit field is encoded in a manner that requires fewer memory device entries and fewer encoded bits per entry than conventional encoding schemes. ... | 11/23/2006 |
| 20060262582 | Physical priority encoder A priority encoder can be used for a Content-Addressable Memory (CAM) device that typically has an array of CAM cells arranged in columns and rows with each row having a match signal indicative that compare data has matched data within the respective row. A priority enc... | 11/23/2006 |
