Class 365/239 - Sequential

Subclass of Class 365 - Static information storage and retrieval
Definition: Subject matter where the memory locations are sequenced
No. of applications: 35
Last issue date: 12/22/2011

Application No.	Application Title	Issue Date
20110310692	SEQUENTIAL-WRITE, RANDOM-READ MEMORY In one embodiment, a method includes, in response to assertion of a write-enable signal at a memory array that comprises a plurality of words, sequentially and at a first clock frequency writing data to the memory array starting at a beginning of the memory array until ...	12/22/2011
20110292743	SEQUENTIAL ACCESS MEMORY ELEMENTS Integrated circuits with sequential access memory cells are provided. A sequential access memory cell may include an inverter-like circuit, an inverter, a preset transistor, an access transistor, and a read circuit. The inverter-like circuit and the inverter are cross-c...	12/01/2011
20110128810	MEMORY DEVICE AND MEMORY CONTROL FOR CONTROLLING THE SAME A memory device includes: a memory cell array which stores two-dimensionally arranged data in a plurality of memory unit regions selected by an address; an internal address control unit which generates an internal address which selects a memory unit region according to ...	06/02/2011
20100172174	SEMICONDUCTOR DEVICE HAVING ARCHITECTURE FOR REDUCING AREA AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME A semiconductor device having an architecture for reducing an area is provided. The semiconductor device includes a memory cell array including a plurality of non-volatile memory cells, a plurality of registers each configured to store pre-fetch unit data, and a write d...	07/08/2010
20100124133	REPLACING DEFECTIVE MEMORY BLOCKS IN RESPONSE TO EXTERNAL ADDRESSES Electronic systems and methods of operating memory devices are provided. In one such embodiment, a memory device receives an external address that addresses a non-defective memory block of a sequence of memory blocks of the memory device in place of a defective memory b...	05/20/2010
20100124132	REPLACING DEFECTIVE COLUMNS OF MEMORY CELLS IN RESPONSE TO EXTERNAL ADDRESSES Electronic systems and methods of operating memory devices are provided. In one such embodiment, a memory device receives an external address that addresses a non-defective column of memory cells of a sequence of columns of memory cells of the memory device in place of ...	05/20/2010
20100110806	SEMICONDUCTOR MEMORY DEVICE A semiconductor memory device includes a plurality of banks, each configured to receive a bank operation control signal and perform predetermined operations in response to the received bank operation control signal, a plurality of bank control blocks, each configured to...	05/06/2010
20100103762	Memory device and method A memory device and method may include separating alternating read and write accesses to different banks of a memory device....	04/29/2010
20100091602	ADDRESS COUNTING CIRCUIT AND SEMICONDUCTOR MEMORY APPARATUS USING THE SAME An address counting circuit includes a counter configured to sequentially count from an initial address in response to a clock signal in order to output counted addresses. The address counting circuit also includes a code conversion unit that is configured to output con...	04/15/2010
20100085830	Sequencing Decoder Circuit A memory-array decoder operably coupled to a memory array comprising a sequence of rows and receiving as input a plurality of address bits includes first and second decoder stages. The first decoder stage selects one or more first rows by decoding a first subset of the ...	04/08/2010
20100008176	Write Leveling Of Memory Units Designed To Receive Access Requests In A Sequential Chained Topology A memory controller provided according to an aspect of the present invention uses a slower clock signal during write leveling compared to when performing write operations thereafter. Due to such use of a slower clock signal, the various desired delays can be determined ...	01/14/2010
20090316512	BLOCK REDUNDANCY IMPLEMENTATION IN HEIRARCHICAL RAM'S The present invention relates to a system and method for providing redundancy in a hierarchically memory, by replacing small blocks in such memory. The present invention provides such redundancy (i.e., replaces such small blocks) by either shifting predecoded lines or u...	12/24/2009
20090285031	SYSTEM AND METHOD FOR SIMULATING AN ASPECT OF A MEMORY CIRCUIT A system and method are provided for simulating an aspect of a memory circuit. Included is an interface circuit that is in communication with a plurality of memory circuits and a system. Such interface circuit is operable to interface the memory circuits and the system ...	11/19/2009
20090245013	Sequential storage circuitry for an integrated circuit Sequential storage circuitry is provided for an integrated circuit, comprising input circuitry, a storage structure, and output circuitry. The input circuitry receives an input data value to the sequential storage circuitry, and generates an internal data value. The inp...	10/01/2009
20090225609	SEMICONDUCTOR MEMORY DEVICE When the input write data is a value of a value greater than the existing data of the memory array 100, the semiconductor memory device enables writing of input write data to the memory array 100. In specific terms, the increment controller 150 read...	09/10/2009
20090207678	Memory writing interference test system and method thereof The present invention is a memory writing interference test system and method thereof. The test system comprises a memory, a progressing unit, a write-in unit, a read-out unit, and a discriminating unit. By sequentially writing data and then reading out the written data...	08/20/2009
20090154254	CLUSTER BASED NON-VOLATILE MEMORY TRANSLATION LAYER An improved non-volatile memory and logical block to physical block address translation method utilizing a cluster based addressing scheme is detailed. The translation of logical blocks/sectors to the physical blocks/sectors is necessary for a non-volatile memory to app...	06/18/2009
20090141582	METHOD FOR RECORDING DATA USING NON-VOLATILE MEMORY AND ELECTRONIC APPARATUS THEREOF A method for recording data using a non-volatile memory and an electronic apparatus thereof are provided. In the present method, a set of input data is provided. Then, a data structure of the input data is transformed into a bitmapping data structure. Afterwards, the in...	06/04/2009
20090141534	DETECTION APPARATUS AND METHOD FOR SEQUENTIALLY PROGRAMMING MEMORY A detection apparatus for sequentially programming a memory is provided. The detection apparatus comprises a current sensor and a programming controller. The current sensor is coupled to a programming source and a memory cell. The current sensor detects change of a prog...	06/04/2009
20090122629	SEQUENTIAL ACCESS MEMORY METHOD A sequential access memory (“SAM”) device, system and method is provided that includes a memory array configured to store a group of bytes on each of a plurality of rows. A plurality of bit-lines transfer each of the group of bytes into and out of the memory array, ...	05/14/2009
20090080280	Electronic memory device An electronic memory device includes a bank of memories provided with a cache, a sequencer for providing physical access to said bank of memories, a physical interface for receiving high level memory access requests, a request manager between the physical interface and ...	03/26/2009
20090046522	METHOD FOR WRITING DATA IN A NON VOLATILE MEMORY UNIT A method for writing data in a non volatile memory unit having memory pages includes a predetermined number of memory cells storing a memory word being a predetermined sequence of digital values. An erase operation erases the memory words in the memory page, setting the...	02/19/2009
20080267001	Protocol Enhancement for PCI Express In a method for enabling a root device to access a plurality of memory locations in an address space in an endpoint device, a first access is sent to the endpoint device by transmitting a first header and a first address. The header includes a continue bit that is set a...	10/30/2008
20080259696	DISTRIBUTED WRITE DATA DRIVERS FOR BURST ACCESS MEMORIES An address strobe latches a first address. A burst cycle increments the address internally with additional address strobes. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating togg...	10/23/2008
20080212379	Semiconductor Memory Device When writing 16-bit write data to the memory array 100 which can store data of 8 bits per 1 row, the semiconductor memory device 10 first writes the upper 8 bits to the 1st write restricted row of the memory array 100. The increment controller 15...	09/04/2008
20080159060	SEQUENTIAL MEMORY AND ACCESSING METHOD THEREOF A method for accessing a memory sequentially. The memory has (m+1) bit lines and at least one row of transistors, wherein m is a positive integer. This method includes the following steps. First, voltage levels of first and second terminals of the transistors are equali...	07/03/2008
20080144410	Redundancy circuit and semiconductor memory device Disclosed is a circuit for deciding whether or not a plural number of redundancy ROM circuits have been programmed in a preset order, with regards to addresses. In at least one of first to n-th redundancy memory circuits, an address to be substituted by a redundant addr...	06/19/2008
20080130393	Semiconductor memory and electronic device A semiconductor memory that reduces the power consumption of a memory cell array without exercising control by a microprocessor. The semiconductor memory comprises a memory cell array, a switch for turning on/off power corresponding to row addresses of the memory cell a...	06/05/2008
20080084782	DATA STORAGE DEVICE AND ITS CONTROLLING METHOD A data storage device includes: a first nonvolatile memory section; a second nonvolatile memory section having a smaller memory capacity than the first nonvolatile memory section; a first write control section that performs a cyclic write control including sequentially ...	04/10/2008
20080025137	SYSTEM AND METHOD FOR SIMULATING AN ASPECT OF A MEMORY CIRCUIT A system and method are provided for simulating an aspect of a memory circuit. Included is an interface circuit that is in communication with a plurality of memory circuits and a system. Such interface circuit is operable to interface the memory circuits and the system ...	01/31/2008
20070165482	SEQUENTIAL ACCESS MEMORY Semiconductor memory devices 10 are each furnished with a memory array 100 having an EEPROM array 101 and a mask ROM array 102. Identifying information for identifying each semiconductor memory device 10 is stored at the beginning thre...	07/19/2007
20070153621	Semiconductor memory device and word line addressing method in which neighboring word lines are discontinuously addressed Disclosed herein are a semiconductor memory device and word line addressing method. The semiconductor memory device comprises a memory array comprising a plurality of word lines arranged in a predetermined sequence, and a word line driver adapted to sequentially address...	07/05/2007
20070091713	ONBOARD DATA STORAGE AND METHOD A semiconductor memory device and an associated method suitable for use in specific applications with predictable memory access pattern, such as in a capsule camera. The memory device takes advantage of the memory access pattern to simplify address processing circuit to...	04/26/2007
20070091715	Semiconductor memory device An internal address generating circuit sequentially generates internal addresses in the burst read operation, with an external address being set as an initial value. A memory core has plural memory cells and sequentially outputs, in response to activation of a column se...	04/26/2007
20060044934	Cluster based non-volatile memory translation layer An improved non-volatile memory and logical block to physical block address translation method utilizing a cluster based addressing scheme is detailed. The translation of logical blocks/sectors to the physical blocks/sectors is necessary for a non-volatile memory to app...	03/02/2006

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Class 365/239 - Sequential