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Ballistic resistant body covering
A ballistic resistant body covering for protecting the torso, groin and neck area from ballistic missiles.
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| Application No. | Application Title | Issue Date |
| 20060092744 | Power supply control circuit and controlling method thereof The present invention provides a power supply control circuit and a control method thereof, capable of securing an accurate operation of a GIO in a burst data transmission having a high compression rate. The power supply control circuit of a semiconductor memory device ... | 05/04/2006 |
| 20060023523 | Integrated semiconductor memory An integrated semiconductor memory includes a memory cell array having memory cells for storing a datum having a first and a second data value. An input datum present at a data terminal is stored multiply in the memory cells of the memory cell array. In order to read ou... | 02/02/2006 |
| 20060023541 | FIFO with multiple data inputs and method thereof A FIFO circuit includes a memory such as a register array having a plurality of storage locations. One or more data inputs can be coupled to the memory for receiving data that is to be stored therein. A control circuit controls the storage of data received from the one ... | 02/02/2006 |
| 20060023526 | Semiconductor memory test apparatus A semiconductor memory test apparatus for testing a device under test using a predetermined test pattern comprises log data generating means for generating log data indicating a test result of the device under test based on output data from the device under test corresp... | 02/02/2006 |
| 20050286339 | Low power sleep mode operation technique for dynamic random access memory (DRAM) devices and integrated circuit devices incorporating embedded DRAM A low power Sleep Mode operation technique for dynamic random access (DRAM) devices and integrated circuit devices incorporating embedded DRAM. By counting clock (CLK) cycles in accordance with the technique disclosed, refresh time (tREF) does not vary with a... | 12/29/2005 |
| 20050254338 | Address generation apparatus and operation apparatus To provide an address generation apparatus and an operation apparatus that is possible to generate a complex address and to suppress an increase of a mounted area even if a bit width of a counter is widened. An address generation apparatus has at least one counter setti... | 11/17/2005 |
| 20050195680 | Semiconductor storage device A semiconductor storage device comprises memory cells having a floating body region and storing data by accumulating or releasing electric charges in or from the floating body region; a memory cell array including a matrix arrangement of said memory cells; a plurality o... | 09/08/2005 |
| 20050099881 | Apparatus for interleave and method thereof An apparatus for interleave includes a serial-parallel circuit which transforms a data form of an input data from serial into parallel and which outputs a plurality of parallel data, a first switch circuit which arranges order of the parallel data based on a first contr... | 05/12/2005 |
| 20050078539 | Circuit and method for controlling a clock synchronizing circuit for low power refresh operation A method and apparatus is provided for idling a clock synchronizing circuit during at least a portion of time during execution of a refresh operation in a memory device. In a memory device receiving an external clock signal, a method and apparatus for executing a refres... | 04/14/2005 |
