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| Application No. | Application Title | Issue Date |
| 20120008437 | COUNTER CIRCUIT, LATENCY COUNTER, SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME, AND DATA PROCESSING SYSTEM To provide a counter circuit capable of accurately counting a high-frequency signal in which hazard or the like is easily generated. There are provided: a frequency dividing circuit that generates first and second frequency dividing clocks, which differ in phase to each... | 01/12/2012 |
| 20110286288 | DYNAMIC ADJUSTMENT OF REFERENCE VOLTAGE IN A COMPUTER MEMORY SYSTEM A method provides improved signal quality in a computer memory system. In one embodiment, a digital signal is generated having a voltage interpreted with respect to a reference voltage. The reference voltage is dynamically adjusted as a function of the traffic intensity... | 11/24/2011 |
| 20110242929 | SEMICONDUCTOR MEMORY APPARATUS A semiconductor memory apparatus includes a counting control circuit and an address counting circuit. The counting control circuit is configured to generate a first counting start signal, a second counting start signal and a counting count signal in response to an auto-... | 10/06/2011 |
| 20110228625 | WRITE COMMAND AND WRITE DATA TIMING CIRCUIT AND METHODS FOR TIMING THE SAME Circuits, memories, and methods for latching a write command and later provided write data including write command and write data timing circuits. One such timing circuit includes internal write command latch to latch an internal write command in response to write comma... | 09/22/2011 |
| 20110158024 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME A semiconductor memory device includes a bank having a plurality of mats, an address counting unit configured to receive an auto-refresh command consecutively applied at predetermined intervals corresponding to a number of the mats, and sequentially count an internal ad... | 06/30/2011 |
| 20110085389 | METHOD AND SYSTEM TO LOWER THE MINIMUM OPERATING VOLTAGE OF A MEMORY ARRAY A method and system to lower the minimum operating voltage of a memory array during read and/or write operations of the memory array. In one embodiment of the invention, the voltage of the read and/or write word line of the memory array is boosted or increased during re... | 04/14/2011 |
| 20110063931 | INTERFACES, CIRCUITS, AND METHODS FOR COMMUNICATING WITH A DOUBLE DATA RATE MEMORY DEVICE An input/output interface reads data from and writes data to a DDR memory. The interface includes data and strobe circuits. The strobe circuit includes preamble logic, a first counter operating with a strobe clock, a second counter operating with an ASIC-generated clock... | 03/17/2011 |
| 20110058445 | LATENCY COUNTER, SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME, AND DATA PROCESSING SYSTEM A latency counter includes an input selecting circuit that selects one of a plurality of signal paths and supplies an internal command to the selected signal path, a shift circuit that switches a correspondence relation between the signal paths and a latch circuit, and ... | 03/10/2011 |
| 20110058444 | LATENCY COUNTER, SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME, AND DATA PROCESSING SYSTEM A latency counter includes a counter circuit and a point-shift FIFO circuit. Latch circuits included in the point-shift FIFO circuit are divided into n groups having wired-OR outputs, and an output of a latch circuit that belongs to a group different from a current grou... | 03/10/2011 |
| 20110058442 | Semiconductor device having ODT function and data processing system including the same To include an AL counter that outputs a second ODT signal after counting a clock signal by an additive latency after receiving a first ODT signal, and a counter control circuit that controls the AL counter such that the second ODT signal having the same logic value as a... | 03/10/2011 |
| 20110058443 | LATENCY COUNTER, SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME, AND DATA PROCESSING SYSTEM A latency counter includes an input selecting circuit that selects one of a plurality of signal paths and supplies an internal command to the selected signal path, a shift circuit that switches a correspondence relation between the signal paths and a latch circuit, and ... | 03/10/2011 |
| 20110051530 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF UPDATING DATA STORED IN THE SEMICONDUCTOR MEMORY DEVICE The semiconductor memory device executes, in address units, operation for inverting data stored in a memory cell designated by an internal address and writing the data in the memory cell and increments the internal address every time inversion writing operation for the ... | 03/03/2011 |
| 20110026339 | Semiconductor memory device performing refresh operation and method of testing the same A semiconductor memory device includes a mask information storage circuit that stores therein mask information indicating an area for which the self refresh operation is not performed among a plurality of areas in a memory cell array, a mask determining circuit that is ... | 02/03/2011 |
| 20110013472 | SEMICONDUCTOR MEMORY DEVICE According to one embodiment, a semiconductor memory device includes a memory array, an address counter, an address detecting circuit and a control circuit. The memory array has a plurality of memory cells arranged at crossing positions of word lines and bit lines. The a... | 01/20/2011 |
| 20100329060 | COUNTER CONTROL SIGNAL GENERATOR AND REFRESH CIRCUIT A counter control signal generator comprises a first pulse signal generator configured to generate a first pulse signal including a pulse generated when a self-refresh period is terminated, a second pulse signal generator configured to generate a second pulse signal inc... | 12/30/2010 |
| 20100321971 | CONTENT ADDRESSABLE MEMORY HAVING SELECTIVELY INTERCONNECTED COUNTER CIRCUITS A content addressable memory (CAM) device includes a plurality of CAM rows, a number of sequencing logic circuits, and a programmable interconnect structure. Each CAM row includes a number of CAM cells to generate a match signal on a match line and includes an enable in... | 12/23/2010 |
| 20100302883 | Method of estimating self refresh period of semiconductor memory device In a method of estimating a self refresh period of a semiconductor memory device according to an exemplary embodiment, a plurality of internal address signals are reset in response to a refresh reset signal. The plurality of internal address signals are sequentially cha... | 12/02/2010 |
| 20100277968 | SEMICONDUCTOR MEMORY DEVICE A semiconductor memory device includes a memory cell array configured of at least a first portion and a second portion each including a plurality of memory cells each with a variable resistor which stores an electrically rewritable resistance value as a data, and a cont... | 11/04/2010 |
| 20100271899 | DIGITAL FILTERS FOR SEMICONDUCTOR DEVICES A memory device that, in certain embodiments, includes a memory element and a digital filter. The digital filter may include a counter and a divider, where the divider is configured to divide a count from the counter by a divisor.... | 10/28/2010 |
| 20100260003 | SEMICONDUCTOR MEMORY APPARATUS AND REFRESH CONTROL METHOD OF THE SAME A semiconductor memory apparatus and refresh control method are presented. The semiconductor memory apparatus includes a memory cell block composed of a multiplicity of floating body cell (FBC) transistors. Each FBC transistor has a gate connected to a word line, a drai... | 10/14/2010 |
| 20100254198 | WRITE COMMAND AND WRITE DATA TIMING CIRCUIT AND METHODS FOR TIMING THE SAME Circuits, memories, and methods for latching a write command and later provided write data including write command and write data timing circuits. One such timing circuit includes internal write command latch to latch an internal write command in response to write comma... | 10/07/2010 |
| 20100246304 | SEMICONDUCTOR MEMORY DEVICE AND REFRESH CONTROL METHOD A semiconductor memory device executes a refresh operation on memory banks, and includes: a command decoder that decodes a command from outside the semiconductor memory device, and outputs a refresh instruction when the command is an auto-refresh command; a refresh comm... | 09/30/2010 |
| 20100195412 | SEMICONDUCTOR DEVICE, METHOD FOR CONTROLLING THE SAME, AND SEMICONDUCTOR SYSTEM The semiconductor device includes a temperature sensor controlled so that temperature measurement is made once at each of a plurality of different reference temperatures at an interval of a preset number of times of refresh operations and a plurality of latch circuits h... | 08/05/2010 |
| 20100188904 | MEMORY VOLTAGE CYCLE ADJUSTMENT The present disclosure includes various method, device, system, and module embodiments for memory cycle voltage adjustment. One such method embodiment includes counting a number of process cycles performed on a first memory block in a memory device. This method embodime... | 07/29/2010 |
| 20100188924 | DATA TRANSFER SYSTEM The invention is directed to decreasing a circuit size of a system in which a plurality of devices or circuit blocks share and use one memory. A system is configured so that a memory block serves as a master and each of circuit blocks serves as a slave, and thus the sla... | 07/29/2010 |
| 20100182864 | SEMICONDUCTOR MEMORY DEVICE REQUIRING REFRESH OPERATION To provide a plurality of memory banks, each of which is divided into a plurality of segments; a bank address register that designates a memory bank that becomes a refresh target; a segment address register that designates a segment that becomes a refresh target; and a ... | 07/22/2010 |
| 20100182862 | Semiconductor memory device and method of controlling auto-refresh Auto-refresh of a semiconductor device may be controlled by setting the number of auto-refresh to be performed in a period of time, based on temperature, when an auto-refresh command is detected.... | 07/22/2010 |
| 20100177589 | SEMICONDUCTOR DEVICE HAVING LATENCY COUNTER A semiconductor device includes a latency setting circuit setting the latency, an input command circuit outputting a normal-phase (reverse-phase) command signal obtained by capturing an input command signal using a normal-phase (reverse-phase) clock, first and second co... | 07/15/2010 |
| 20100165773 | SEMICONDUCTOR MEMORY DEVICE FOR SELF REFRESH AND MEMORY SYSTEM HAVING THE SAME A semiconductor memory device includes a memory core unit including a memory cell array including a plurality of memory cells and a sense amplifier to sense and amplify data of the plurality of memory cells, and a self refresh control unit to apply at least one first co... | 07/01/2010 |
| 20100169740 | ACCELERATING PHASE CHANGE MEMORY WRITES In a phase change memory, the memory array may be written in relatively small chunks. The writing of data to the array and, particularly, the writing of set data, may be accelerated using a hardware accelerator. The hardware accelerator may include an edge detector whic... | 07/01/2010 |
| 20100165769 | SEMICONDUCTOR MEMORY DEVICE HAVING AUTO-PRECHARGE FUNCTION To provide a semiconductor memory device including: a first clock generation circuit and a second clock generation circuit that generate a first internal clock and a second internal clock, respectively; a latency counter that counts latency synchronously with the first ... | 07/01/2010 |
| 20100165732 | FLASH MEMORY APPARATUS AND READ OPERATION CONTROL METHOD THEREFOR A flash memory apparatus of an embodiment is configured to include a flash memory including a plurality of blocks and a read operation control circuit determining whether to replace a block in accordance with the number of times a read process is performed for each bloc... | 07/01/2010 |
| 20100157717 | SEMICONDUCTOR INTEGRATED CIRCUIT CAPABLE OF CONTROLLING READ COMMAND The semiconductor integrated circuit includes a command decoder, a shift register unit and a command address latch unit. The command decoder is responsive to an external command defining write and read modes and configured to provide a write command or a read command ac... | 06/24/2010 |
| 20100110810 | SEMICONDUCTOR MEMORY DEVICE AND SYSTEM A semiconductor memory device includes a memory cell array including primary word lines and one or more redundant word lines, a timing signal generating circuit configured to generate a refresh timing signal comprised of a series of pulses arranged at constant intervals... | 05/06/2010 |
| 20100110817 | Semiconductor device and refreshing method A semiconductor device comprising a word line wired on a memory bank, a memory cell storing data provided in correspondence with the word line and a sense amplifier provided in correspondence with the word line, refreshing the memory cell corresponding to the word line ... | 05/06/2010 |
| 20100103740 | Nonvolatile Memory Device, Methods of Programming the Nonvolatile Memory Device and Memory System Including the Same A nonvolatile memory device is provided. A counter counts an amount of data to be program-inhibited among data to be written to memory cells to provide a first count value. The counter also counts an amount of program-inhibited data among data written to the memory cell... | 04/29/2010 |
| 20100097853 | Jeet memory cell A memory cell (FIG. 6A) compatible with dynamic random access memories (DRAM) and static random access memories (SRAM) is disclosed. The memory cell includes a first junction field effect transistor (600) having a first conductivity type. A second junction... | 04/22/2010 |
| 20100091602 | ADDRESS COUNTING CIRCUIT AND SEMICONDUCTOR MEMORY APPARATUS USING THE SAME An address counting circuit includes a counter configured to sequentially count from an initial address in response to a clock signal in order to output counted addresses. The address counting circuit also includes a code conversion unit that is configured to output con... | 04/15/2010 |
| 20100074042 | SEMICONDUCTOR MEMORY DEVICE A memory may includes: word lines; bit lines; memory array blocks including memory cells, each memory array block being a unit of a data read operation or a data write operation; a row decoder configured to selectively drive the word lines; sense amplifiers configured t... | 03/25/2010 |
| 20100067303 | FLASH MEMORY DEVICE CAPABLE OF REDUCED PROGRAMMING TIME A flash memory device comprising a high voltage generator circuit that is adapted to supply a program voltage having a target voltage to a selected word line is provided. The flash memory device is adapted to terminate the program interval in accordance with when the pr... | 03/18/2010 |
