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| Application No. | Application Title | Issue Date |
| 20080002513 | Method and apparatus for latent fault memory scrub in memory intensive computer hardware A method for operating a memory checker in a command monitoring architecture comprising at least two processing lanes comprises a first step of receiving a command to activate a first test mode. The first test mode comprises an initial step of inverting data read from a... | 01/03/2008 |
| 20080002499 | Semiconductor memory apparatus having plurality of sense amplifier arrays having different activation timing A semiconductor memory apparatus according to an embodiment of the present invention includes a plurality of cell mats each having a plurality of cells, a plurality of sense amplifier arrays, each having a plurality of sense amplifiers for sensing the cells in response ... | 01/03/2008 |
| 20080002516 | Memory Device Having a Delay Locked Loop and Multiple Power Modes A single chip dynamic random access memory has a memory core, including dynamic random access memory cells, and a clock receiver circuit to receive an external clock signal. A delay locked loop circuit is coupled to the clock receiver circuit. In a first power mode, the... | 01/03/2008 |
| 20080002515 | MEMORY WITH ALTERABLE COLUMN SELECTION TIME A memory contains memory cells and is clock-controlled on the basis of a basic clock signal at the frequency fc, wherein a chosen memory cell is accessed by closing an addressed column selection switch. The memory has a pulse generator to produce a column sel... | 01/03/2008 |
| 20080002514 | Semiconductor memory device and driving method thereof A semiconductor memory device includes: a variable delay for delaying a delay locked loop (DLL) clock by a predetermined delay time to output a delayed DLL clock; an output driver for outputting data and data strobe signal in response to the delayed DLL clock; and a cal... | 01/03/2008 |
| 20070297255 | Semiconductor memory tester There is implemented a semiconductor memory tester capable of efficiently conducting a test on a fast memory by programming according to parameters of a device without being attended by complex program handling. The semiconductor memory tester for determining pass/fail ... | 12/27/2007 |
| 20070297266 | SYNCHRONOUS GLOBAL CONTROLLER FOR ENHANCED PIPELINING The present invention relates to a system and method for processing the read and write operations in a memory architecture. The system processing the read and write operations includes at least one local memory block and a synchronously controlled global controller coup... | 12/27/2007 |
| 20070297250 | Data processing apparatus and method using FIFO device In a data processing apparatus and method using a first-in first-out (FIFO), the data processing apparatus includes a first sampling circuit, a delay circuit, and a FIFO device. The first sampling circuit samples a logic state of input data in response to a first edge o... | 12/27/2007 |
| 20070297270 | Semiconductor integrated circuit device The present invention provides a technique capable of achieving area reduction on a semiconductor integrated circuit device mounted with a time sharing virtual multi port memory or the like. By providing a configuration including a single port memory, data latch circuit... | 12/27/2007 |
| 20070291554 | Memory with Clock-Controlled Memory Access and Method of Operating the Same An integrated circuit memory with clock-controlled memory access includes at least one data connection to input/output data, a memory cell array including memory cells to store data, a clock generator circuit to generate a clock signal, a memory circuit to store data, a... | 12/20/2007 |
| 20070291553 | DATA OUTPUT CIRCUITS FOR AN INTEGRATED CIRCUIT MEMORY DEVICE IN WHICH DATA IS OUTPUT RESPONSIVE TO SELECTIVE INVOCATION OF A PLURALITY OF CLOCK SIGNALS, AND METHODS OF OPERATING THE SAME A data output circuit for an integrated circuit memory device includes a control circuit that is configured to generate a plurality of clock signals responsive to at least a portion of a memory column address, and a multiplexer circuit that is configured to output memor... | 12/20/2007 |
| 20070291568 | Apparatus and method for controlling refresh operation of semiconductor integrated circuit A semiconductor memory integrated circuit for controlling a refresh operation includes: a first period generating unit that generates a first periodic signal having an uniformed period; a second period generating unit that generates a second periodic signal according to... | 12/20/2007 |
| 20070291576 | ADDRESS LATCH CIRCUIT OF SEMICONDUCTOR MEMORY DEVICE An address latch circuit of a semiconductor memory device is provided. The address latch circuit includes a first address latch part, which latches a first address signal fed from outside according to a first address latch signal and outputs a second address signal. An ... | 12/20/2007 |
| 20070291577 | SYSTEM WITH CONTROLLER AND MEMORY According to the system of the present invention, data (DQ) signals are outputted/received between a controller 100 and a memory 200 based on a data strobe signal sent out from the controller 100. The data strobe signal is independently and complete... | 12/20/2007 |
| 20070286012 | METHOD FOR CONTROLLING DATA OUTPUT TIMING OF MEMORY DEVICE AND DEVICE THEREFOR Disclosed is a device for controlling data output of a memory device using a DLL clock signal, the device comprising: an output driver for outputting data; and a CAS latency control unit for generating a signal adjusting an operation timing of the output driver dependin... | 12/13/2007 |
| 20070280034 | System and method for performing low power dynamic trimming A system and method for performing dynamic trimming. Specifically, the system comprises a clock for generating a reference clock signal. The reference clock signal comprises a first frequency that is a factor of a second frequency of a signal (e.g., data clock signal fr... | 12/06/2007 |
| 20070280032 | Built-in system and method for testing integrated circuit timing parameters A built-in self-test system for a dynamic random access memory device using a data output register of the memory device to apply test signals to data bus terminals and a data strobe terminal of the memory device responsive to respective clock signals. The clock signal a... | 12/06/2007 |
| 20070280033 | METHODS AND DEVICES FOR REGULATING THE TIMING OF CONTROL SIGNALS IN INTEGRATED CIRCUIT MEMORY DEVICES A method of regulating timing of control signals in an integrated circuit memory device includes generating a pulse signal having a pulse width representing a time period between a rising edge of a first control signal and a rising edge of a second control signal that i... | 12/06/2007 |
| 20070268775 | NAND system with a data write frequency greater than a command-and-address-load frequency The invention provides methods and apparatus. A NAND flash memory device receives command and address signals at a first frequency and a data signal at a second frequency that is greater than the first frequency. ... | 11/22/2007 |
| 20070268760 | SEMICONDUCTOR MEMORY IN WHICH FUSE DATA TRANSFER PATH IN MEMORY MACRO IS BRANCHED A semiconductor device includes a memory macro and fuse box. The fuse box includes a clock generator, a plurality of first data latch circuits which latch fuse data, and serially transfer the fuse data upon receiving transfer clocks, and a clock counter which counts the... | 11/22/2007 |
| 20070268777 | Integrated Semiconductor Memory Device with Clock Generation A memory device can be operated in a first operating state and a second operating state, where read access to memory cells can be performed in the first operating state. The memory device includes an activatable clock generator circuit to generate a clock signal. The cl... | 11/22/2007 |
| 20070268776 | SEMICONDUCTOR MEMORY DEVICE AND TEST METHOD THEREOF When a predetermined code is set to a mode register, a switching signal generating circuit is activated, and a switching signal TCLKE becomes at a high level. When the switching signal TCLKE becomes at a high level, input data supplied from a data input and output termi... | 11/22/2007 |
| 20070268772 | Semiconductor memory and operating method of same An operation control circuit carries out a first access operation upon receipt of a first access command during activation of a chip enable signal, and carries out a second access operation accessing a memory core in a shorter time than the first access operation, upon ... | 11/22/2007 |
| 20070263460 | DLL with reduced size and semiconductor memory device including DLL and locking operation method of the same A DLL with a reduced size, a semiconductor memory device including the DLL and a locking operation method of the DLL that includes a phase detector, a delay line, a delay controller, a delay circuit and an output buffer. The phase detector detects phase difference betwe... | 11/15/2007 |
| 20070263475 | USING COMMON MODE DIFFERENTIAL DATA SIGNALS OF DDR2 SDRAM FOR CONTROL SIGNAL TRANSMISSION A double-data-rate two synchronous dynamic random access (DDR2) memory circuit includes a low-speed input path and a high-speed input path coupled thereto by an input coupling and forming a common input, the common input coupled to a memory core, the memory core having ... | 11/15/2007 |
| 20070258304 | Method and System for Preventing Noise Disturbance in High Speed, Low Power Memory A memory device comprises a memory cell and a sense amplifier which has a sensing interval. An output circuit is coupled to the sense amplifier and responsive to a clock signal to accept the signal from the sense amplifier. A first source of timing signals generates a f... | 11/08/2007 |
| 20070253277 | Semiconductor integrated circuit device, data processing system and memory system The data for being processed are transmitted by utilizing a daisy chain constitution using a plurality of semiconductor integrated circuit devices each having an input terminal for receiving an input signal containing any one of an instruction, a data, a position where ... | 11/01/2007 |
| 20070253276 | Method of preventing dielectric breakdown of semiconductor device and semiconductor device preventing dielectric breakdown A semiconductor device that prevents a build-up of electrostatic charge in a dummy pad is provided. The semiconductor device may contain an internal circuit formed on a semiconductor substrate and the dummy pad which is not electrically connected to the internal circuit... | 11/01/2007 |
| 20070247962 | Semiconductor integrated circuit device, data processing system and memory system The data for being processed are transmitted by utilizing a daisy chain constitution using a plurality of semiconductor integrated circuit devices each having an input terminal for receiving an input signal containing any one of an instruction, a data, a position where ... | 10/25/2007 |
| 20070247961 | MEMORY CONTROLLER WITH STAGGERED REQUEST SIGNAL OUTPUT A memory controller having a time-staggered request signal output. A first timing signal is generated with a phase offset relative to a first clock signal in accordance with a first programmed value, and a second timing signal is generated with a phase offset relative t... | 10/25/2007 |
| 20070247934 | High-Performance Flash Memory Data Transfer A flash memory system including a flash memory device and a controller, operable according to an advanced data transfer mode is disclosed. The flash memory device is operable both in a “legacy” mode, in which read data is presented by the memory synchronously with e... | 10/25/2007 |
| 20070247960 | System and method to synchronize signals in individual integrated circuit components A synchronous output signal generated by an integrated circuit (IC) component is synchronized to an applied clock signal for each individual IC component. A variable feedback delay in the IC component is incrementally altered to alter the phase skew between the clock si... | 10/25/2007 |
| 20070242556 | Semiconductor device using dynamic circuit The present invention provides a semiconductor device having a plurality of functional blocks and a select signal generation circuit for supplying a select signal to a functional block to be operated out of the plurality of blocks. A clock generation unit in the functio... | 10/18/2007 |
| 20070237021 | Memory with clocked sense amplifier In one form a memory and method thereof has a memory array having a plurality of columns of bit lines and a plurality of intersecting rows of word lines. Control circuitry is coupled to the memory array for successively accessing predetermined bit locations in the memor... | 10/11/2007 |
| 20070230266 | Methods of DDR receiver read re-synchronization One embodiment of the invention provides a method for reading data. The method includes generating two or more pulses from a first clock signal by which the data to be read is received, using each generated pulse to latch data received at a corresponding time, and detec... | 10/04/2007 |
| 20070211557 | FLASH MEMORY CONTROLLER An apparatus for controlling a flash memory device which includes a signal generator for generating a clock signal at an operation, a first buffer for outputting the clock signal to the flash memory device as a clock enable signal a second buffer for receiving data from... | 09/13/2007 |
| 20070211559 | COMPUTER SYSTEM WITH NAND FLASH MEMORY FOR BOOTING AND STORAGE A computer system includes a system controller with a central processing unit and a memory bus controller operating in a first interface mode; a system memory connected with the system controller through the system bus; a NAND flash memory for storing a system driving c... | 09/13/2007 |
| 20070211558 | Circuit and method for detecting synchronous mode in a semiconductor memory apparatus A circuit for detecting synchronous mode in a semiconductor memory apparatus includes a control unit that controls the driving of a clock according to whether or not a valid address signal is enabled. A driving unit drives the clock according to the control of the contr... | 09/13/2007 |
| 20070211556 | Input latency control circuit, a semiconductor memory device including an input latency control circuit and method thereof An input latency control circuit, a semiconductor memory device including an input latency control circuit and method thereof are provided. The example semiconductor memory device may include a clock buffer configured to generate an internal clock signal based on an ext... | 09/13/2007 |
| 20070211555 | Address buffer and method for buffering address in semiconductor memory apparatus An address buffer in a semiconductor memory apparatus includes: an address input unit that generates a first latch input address from a buffering enable signal and an input address. A clock synchronizing unit generates a second latch input address from the first latch i... | 09/13/2007 |
