Bizarre Patents
Behavior Modification Wristwatch
A wristwatch including a watch band and a watch body having an octagon shaped perimeter and being red in color and having the word STOP thereon to resemble a stop sign.
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| Application No. | Application Title | Issue Date |
| 20120127772 | LOW POWER SRAM BASED CONTENT ADDRESSABLE MEMORY An apparatus comprising a memory array and a plurality of processing circuits. The memory array may be configured to store a plurality of data bits in a plurality of rows and a plurality of columns. A plurality of data words may be stored in a respective plurality of th... | 05/24/2012 |
| 20120106284 | MEMORY POWER SUPPLY CIRCUIT A memory power supply circuit includes a memory module, a micro control unit (MCU), a phase switch circuit, and a multi-phase pulse-width modulation (PWM) controller. The MCU is operable to determine required current to be supplied to the memory module and output corres... | 05/03/2012 |
| 20120106285 | CIRCUITS AND METHODS FOR REDUCING MINIMUM SUPPLY FOR REGISTER FILE CELLS A register file employing a shared supply structure to improve the minimum supply voltage.... | 05/03/2012 |
| 20120081987 | SUPPLY VOLTAGE DISTRIBUTION SYSTEM WITH REDUCED RESISTANCE FOR SEMICONDUCTOR DEVICES A supply voltage distribution system for distributing a supply voltage through a semiconductor device, the supply voltage distribution system comprising:
| 04/05/2012 |
| 20120069636 | STATIC RANDOM ACCESS MEMORY (SRAM) HAVING BIT CELLS ACCESSIBLE BY SEPARATE READ AND WRITE PATHS A method is for reading a first bit cell of a static random access memory in which the static random access memory has a first plurality of bit cells including the first bit cell. Each bit cell of the first plurality of bit cells includes a cross coupled pair of inverte... | 03/22/2012 |
| 20120054426 | System and Method of Reducing Power Usage of a Content Addressable Memory A system is disclosed that includes a content addressable memory and an input register coupled to the content addressable memory. The input register can store a data word and the content addressable memory determines if the data word exists in the content addressable me... | 03/01/2012 |
| 20120044779 | DATA-AWARE DYNAMIC SUPPLY RANDOM ACCESS MEMORY A Random Access Memory (RAM) with a plurality of cells is provided. In an embodiment, the cells of a same column are coupled to a same pair of bit-lines and are associated to a same power controller. Each cell has two inverters; the power controller has two power-switch... | 02/23/2012 |
| 20120039142 | SCALEABLE LOOK-UP TABLE BASED MEMORY An integrated circuit having a logic element that includes an array of storage elements convertibly functioning as either a configuration random access memory (CRAM) or a static random access memory (SRAM) is provided. The logic element includes first and second pairs o... | 02/16/2012 |
| 20120033521 | Semiconductor apparatus and its control method Semiconductor apparatus includes first power supply line and second power supply line, first sub power supply line, first switch circuit, first logic circuit and first control circuit. First switch circuit is disposed between first power supply line and first sub power ... | 02/09/2012 |
| 20120033520 | MEMORY WITH LOW VOLTAGE MODE OPERATION A memory comprising memory cells wherein the memory is configured to operate in a normal voltage mode and a low voltage mode. The method includes during the normal voltage mode, operating the memory cells at a first voltage across each of the memory cells. The method fu... | 02/09/2012 |
| 20120026805 | SRAM BITCELL DATA RETENTION CONTROL FOR LEAKAGE OPTIMIZATION An integrated circuit includes a static random access memory (SRAM) array coupled to a first voltage supply node and a second voltage supply node. The first and second voltage supply nodes provide a retention voltage across the SRAM array. A current limiter is disposed ... | 02/02/2012 |
| 20120014201 | DUAL RAIL MEMORY A memory comprising: a plurality of memory cells arranged in a plurality of rows and a plurality of columns. A column of the plurality of columns including a first power supply node configured to provide a first voltage, a second power supply node configured to provide ... | 01/19/2012 |
| 20120008377 | STATIC RANDOM ACCESS MEMORY WITH DATA CONTROLLED POWER SUPPLY A static random access memory with data controlled power supply, which comprises a memory cell circuit and at least one Write-assist circuit, for providing power to the memory cell circuit according to data to be written to the memory cell circuit.... | 01/12/2012 |
| 20120008427 | Semiconductor Memory Device To Reduce Off-Current In Standby Mode A semiconductor memory device capable of reducing off-current in a standby mode is provided. The semiconductor memory device includes an enable signal generating unit configured to receive a plurality of address decoding signals and generate a first enable signal to sel... | 01/12/2012 |
| 20120002498 | NONVOLATILE MEMORY, DATA PROCESSING APPARATUS, AND MICROCOMPUTER APPLICATION SYSTEM Operational stability of the nonvolatile memory in plural power supply voltage modes set up in advance corresponding to the power supply voltage level is realized. A nonvolatile memory is configured with a memory array, a charge pump, a distributor for selecting an outp... | 01/05/2012 |
| 20110310663 | METHOD FOR DRIVING STORAGE ELEMENT AND STORAGE DEVICE Disclosed herein is a method for driving a storage element that has a plurality of magnetic layers and performs recording by utilizing spin torque magnetization reversal, the method including applying a pulse voltage having reverse polarity of polarity of a recording pu... | 12/22/2011 |
| 20110310689 | POWER SOURCE AND POWER SOURCE CONTROL CIRCUIT Power sources, backup power circuits, power source control circuits, data storage devices, and methods relating to controlling application of power to a node are disclosed. An example power source includes an input, backup power source, and a backup power source control... | 12/22/2011 |
| 20110310690 | VOLTAGE REGULATORS, MEMORY CIRCUITS, AND OPERATING METHODS THEREOF A voltage regulator includes an output stage electrically coupled with an output end of the voltage regulator. The output stage includes at least one transistor having a bulk and a drain. At least one back-bias circuit is electrically coupled with the bulk of the at lea... | 12/22/2011 |
| 20110305100 | SEMICONDUCTOR MEMORY DEVICE A semiconductor memory device including a plurality of layers each including a memory cell array and which are stacked over each other; and at least one power plane for supplying power to the layers. The power plane includes a region to which a power voltage is applied ... | 12/15/2011 |
| 20110286292 | METHOD OF FORMING A UNIQUE NUMBER A unique number is formed with logic states from a static random access memory (SRAM), which is laid out to be balanced so that memory cells within the SRAM assume a non-random logic state when power is applied to the SRAM. The unique number is formed by grounding the w... | 11/24/2011 |
| 20110286294 | METHOD OF FORMING A UNIQUE NUMBER A unique number is formed with logic states from a static random access memory (SRAM), which is laid out to be balanced so that memory cells within the SRAM assume a non-random logic state when power is applied to the SRAM. The unique number is formed by grounding the w... | 11/24/2011 |
| 20110286293 | METHOD OF FORMING A UNIQUE NUMBER A unique number is formed with logic states from a static random access memory (SRAM), which is laid out to be balanced so that memory cells within the SRAM assume a non-random logic state when power is applied to the SRAM. The unique number is formed by grounding the w... | 11/24/2011 |
| 20110280094 | Boost Cell Supply Write Assist A method of increasing a drain to source voltage measured at an access pass-gate to a SRAM circuit in a SRAM memory array, including increasing a low voltage from a low voltage source powering said SRAM circuit, and increasing a high voltage from a high voltage source p... | 11/17/2011 |
| 20110280095 | MEMORY CIRCUITS HAVING A PLURALITY OF KEEPERS A memory circuit includes a first plurality of memory arrays disposed in a column fashion. The memory circuit includes a first plurality of keepers each of which is electrically coupled with a corresponding one of the first plurality of memory arrays. A first current li... | 11/17/2011 |
| 20110280088 | SINGLE SUPPLY SUB VDD BITLINE PRECHARGE SRAM AND METHOD FOR LEVEL SHIFTING A reduced bitline precharge level has been found to increase the SRAM Beta ratio, thus improving the stability margin. The precharge level is also supplied to Sense amplifier, write driver, and source voltages for control signals. In the sense amplifier, the lower prech... | 11/17/2011 |
| 20110280096 | MEMORY CIRCUITS HAVING A PLURALITY OF KEEPERS A memory circuit includes a first plurality of memory arrays disposed in a column fashion. The memory circuit includes a first plurality of keepers each of which is electrically coupled with a corresponding one of the first plurality of memory arrays. A first current li... | 11/17/2011 |
| 20110273939 | NONVOLATILE MEMORY DEVICE A nonvolatile memory device includes a nonvolatile memory and a controller unit for the nonvolatile memory. The nonvolatile memory and the controller unit include a first logic section and a second logic section, respectively. The nonvolatile memory includes a voltage d... | 11/10/2011 |
| 20110273951 | MEMORY CIRCUIT AND METHOD FOR CONTROLLING MEMORY CIRCUIT A memory circuit includes a first memory array, a second memory array and a switch module, wherein the first memory array has a first node and a second node, the second memory array has a third node and a fourth node, the first node is coupled to a first supply voltage,... | 11/10/2011 |
| 20110273952 | SEMICONDUCTOR MEMORY DEVICE THAT CAN STABLY PERFORM WRITING AND READING WITHOUT INCREASING CURRENT CONSUMPTION EVEN WITH A LOW POWER SUPPLY VOLTAGE Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supp... | 11/10/2011 |
| 20110267880 | MEMORY CIRCUITS HAVING A DIODE-CONNECTED TRANSISTOR WITH BACK-BIASED CONTROL A memory circuit includes at least one memory array. At least one sleep transistor is electrically coupled between the at least one memory array and a first power line for providing a first power voltage. At least one diode-connected transistor is electrically coupled b... | 11/03/2011 |
| 20110267875 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR TESTING THE SAME A semiconductor memory device includes a memory cell array configured to include a plurality of memory cells, a plurality of bit lines respectively coupled to the plurality of memory cells, a first power-supply voltage supplying circuit configured to provide a first pow... | 11/03/2011 |
| 20110267916 | VDD PRE-SET OF DIRECT SENSE DRAM A direct sense memory array architecture and method of operation includes a plurality of memory cells where a bit-line restore voltage level is optimized to reduce memory cell leakage during a first inactive period, and a bit-line preset voltage level is optimized for s... | 11/03/2011 |
| 20110261630 | SEMICONDUCTOR DEVICE A semiconductor device compares potential AF_G at an end of an anti-fuse element with potential VPPR. If potential AF_G is equal to or higher than potential VPPR, then the semiconductor device boosts potential VPPSVT of a power supply line that is connected to the end o... | 10/27/2011 |
| 20110261628 | 256 Meg dynamic random access memory A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in th... | 10/27/2011 |
| 20110255356 | SEMICONDUCTOR MEMORY DEVICE AND OPERATION METHOD THEREOF A semiconductor memory device includes a clock synchronizing unit for receiving a first power voltage through a first power voltage terminal, and an additional power voltage providing unit for additionally providing a second power voltage to the first power voltage term... | 10/20/2011 |
| 20110255361 | MULTI-PORT MEMORY HAVING A VARIABLE NUMBER OF USED WRITE PORTS A multi-port memory is operated according to a method. Data is written, in a first mode, to a storage node of a memory cell from a first port through a first conductance. The first mode is characterized by a power supply voltage being applied at a power node at a first ... | 10/20/2011 |
| 20110242904 | Read Only Memory and Operating Method Thereof A read only memory (ROM) and an operating method thereof are provided. The read only memory includes: a control circuit, powered by a first power source for outputting a control signal within a first voltage range; a voltage shifter, for expanding the amplitude of the c... | 10/06/2011 |
| 20110242906 | DUAL FUNCTION COMPATIBLE NON-VOLATILE MEMORY DEVICE A dual function memory device architecture compatible with asynchronous operation and synchronous serial operation. The dual function memory device architecture includes one set of physical ports having two different functional assignments. Coupled between the physical ... | 10/06/2011 |
| 20110235443 | VOLTAGE STABILIZATION CIRCUIT AND SEMICONDUCTOR MEMORY APPARATUS USING THE SAME A voltage stabilization circuit of a semiconductor memory apparatus includes an operation speed detecting unit configured to detect an operation speed of the semiconductor memory apparatus to generate a detection signal, and a voltage line controlling unit configured to... | 09/29/2011 |
| 20110235445 | METHOD AND SYSTEM TO LOWER THE MINIMUM OPERATING VOLTAGE OF REGISTER FILES A method and system to lower the minimum operating voltage of a register file without increasing the area of each bit cell of the register file. In one embodiment of the invention, the register file is coupled to logic that reduces the contention between the NMOS device... | 09/29/2011 |
