Class 365/207 - Differential sensing

Subclass of Class 365 - Static information storage and retrieval
Definition: Subject matter where the circuit used is of the differential
No. of applications: 503
Last issue date: 05/24/2012

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Application No.	Application Title	Issue Date
20120127811	TIMING GENERATION CIRCUIT, SEMICONDUCTOR STORAGE DEVICE AND TIMING GENERATION METHOD According to an embodiment, a semiconductor storage device includes a memory cell array, a plurality of sense amplifiers and a timing generation circuit. The memory cell array includes a plurality of word lines, a plurality of bit lines crossing the plurality of word li...	05/24/2012
20120106281	SEMICONDUCTOR MEMORY DEVICES AND SEMICONDUCTOR MEMORY SYSTEMS A semiconductor memory device includes at least one memory cell block and at least one connection unit. The at least one memory cell block has a first region including at least one first memory cell connected to a first bit line, and a second region including at least o...	05/03/2012
20120081974	INPUT-OUTPUT LINE SENSE AMPLIFIER HAVING ADJUSTABLE OUTPUT DRIVE CAPABILITY An input-output line sense amplifier configured to drive input data signals over an input-output signal line to an output driver circuit, the input-output line sense amplifier having an output driver stage having a plurality of different programmable output drive capaci...	04/05/2012
20120081985	SEMICONDUCTOR APPARATUS A semiconductor apparatus includes: odd and even sub word line driving units configured to selectively drive odd sub word lines and even sub word lines among a plurality of sub word lines; a bit line sense amplifier including a plurality of sense amplifier driving lines...	04/05/2012
20120081986	Semiconductor Devices, Operating Methods Thereof, And Memory Systems Including The Same At least one example embodiment discloses a semiconductor device. The semiconductor device includes a first sense amplifier selectively connected between a first bit line and a second bit line, a second sense amplifier selectively connected between the first bit line an...	04/05/2012
20120069692	SEMICONDUCTOR DEVICE A data input buffer is changed from an inactive to an active state after the reception of instruction for a write operation effected on a memory unit. The input buffer is a differential input buffer having interface specs based on SSTL, for example, which is brought to ...	03/22/2012
20120039144	Semiconductor device with shortened data read time A semiconductor device includes: a plurality of memory cell arrays arranged along a predetermined direction; a plurality of bit lines to read data stored in a plurality of memory elements; a plurality of sense amplifier sections that amplify potentials appearing on sele...	02/16/2012
20120039143	SENSE AMPLIFIER WITH ADJUSTABLE BACK BIAS A circuit having a sensing circuit and at least one of a first node and a second node is described. The sensing circuit includes a pair of a first type transistors and a pair of a second type transistors. Each transistor of the pair of the first type transistors is coup...	02/16/2012
20120033518	CURRENT SINK SYSTEM FOR SOURCE-SIDE SENSING Source-side sensing techniques described herein determine the data value stored in a memory cell based on the difference in current between the read current from the source terminal of the memory cell and a sink current drawn from the read current. The sink current is d...	02/09/2012
20120026818	Split Bit Line Architecture Circuits and Methods for Memory Devices Apparatus and methods for providing a high density memory array with reduced read access time are disclosed. Multiple split bit lines are arranged along columns of adjacent memory bit cells. A multiple input sense amplifier is coupled to the multiple split bit lines. Th...	02/02/2012
20120020176	GENERATING AND AMPLIFYING DIFFERENTIAL SIGNALS Some embodiments regard a circuit comprising: a first left transistor having a first left drain, a first left gate, and a first left source; a second left transistor having a second left drain, a second left gate, and a second left source; a third left transistor having...	01/26/2012
20120014168	Dual Stage Sensing for Non-Volatile Memory A method and apparatus for accessing a non-volatile memory cell. In some embodiments, a memory block provides a plurality of memory cells arranged into rows and columns. A read circuit is configured to read a selected row of the memory block by concurrently applying a c...	01/19/2012
20110317506	Method for Asymmetric Sense Amplifier Methods for determining the state of memory cells include using an asymmetric sense amplifier. The methods include sensing the voltages on bit line (BL) and bit line bar (BLB) signals by coupling the BL to a first output node of an imbalanced cross-coupled latch (ICL), ...	12/29/2011
20110317497	NON-VOLATILE MEMORY DEVICE A non-volatile memory device for measuring a read current of a unit cell is disclosed. The non-volatile memory device includes a unit cell configured to read or write data, a column switching unit configured to select the unit cell in response to a column selection sign...	12/29/2011
20110310688	CURRENT MODE DATA SENSING AND PROPAGATION USING VOLTAGE AMPLIFIER A method and a circuit for current mode data sensing and propagation by using voltage amplifier are provided. Example embodiments may include providing an output signal from a voltage amplifier in response to the voltage amplifier receiving an input signal. The method m...	12/22/2011
20110310687	CURRENT SENSE AMPLIFIERS, MEMORY DEVICES AND METHODS A current sense amplifier may include one or more clamping circuits coupled between differential output nodes of the amplifier. The clamping circuits may be enabled during at least a portion of the time that the sense amplifier is sensing the state of a memory cell coup...	12/22/2011
20110305098	SEMICONDUCTOR MEMORY DEVICE WITH SENSE AMPLIFIER AND BITLINE ISOLATION A semiconductor memory device, including: a memory cell connected to a first bitline and associated with a second bitline; a sense amplifier, including a first input/output node and a second input/output node; and an isolator connected to the bitlines and to the input/o...	12/15/2011
20110292750	BIT LINE SENSE AMPLIFIER CONTROL CIRCUIT AND SEMICONDUCTOR MEMORY APPARATUS HAVING THE SAME A bit line sense amplifier control circuit is configured to drive a bit line sense amplifier according to a first sense amplifier enable signal and a second sense amplifier enable signal, wherein the driving force of the bit line sense amplifier is changed in response t...	12/01/2011
20110286259	Reading Memory Elements Within a Crossbar Array A method for reading the state of a memory element within a crossbar memory array includes storing a first electric current sensed from a half-selected target memory element within the crossbar memory array; and outputting a final electric current based on the stored fi...	11/24/2011
20110261637	INCREASED DRAM-ARRAY THROUGHPUT USING INACTIVE BITLINES A memory device with increased communication bandwidth is described. In this memory device, control logic routes data signals from a memory array using inactive bitlines in response to a read command. These data signals are then placed on an adjacent unused input/output...	10/27/2011
20110261610	NONVOLATILE MEMORY DEVICE AND METHOD FOR CONTROLLING THE SAME A nonvolatile memory device includes a cell array including a plurality of phase change memory cells, a switching unit configured to select any one of the plurality of phase change memory cells, a clamping unit coupled between the switching unit and a sensing line and c...	10/27/2011
20110261631	SEMICONDUCTOR DEVICE AND DATA PROCESSING SYSTEM COMPRISING SEMICONDUCTOR DEVICE A semiconductor device comprises a sense amplifier circuit amplifying a signal transmitted through the bit line, first/second data lines transmitting the signal amplified by the sense amplifier circuit, a read amplifier circuit driven by a first voltage and amplifying t...	10/27/2011
20110255359	Sense-Amplification With Offset Cancellation For Static Random Access Memories An offset cancellation scheme for sense amplification is described. The scheme consists of group of transistors which are selectively coupled to high and low voltage levels via multi-phase timing. This results in a voltage level on nodes of interest which are a function...	10/20/2011
20110242920	VOLTAGE SENSING CIRCUIT CAPABLE OF CONTROLLING A PUMP VOLTAGE STABLY GENERATED IN A LOW VOLTAGE ENVIRONMENT Herein, a voltage sensing circuit, which is capable of controlling a pumping voltage to be stably generated in a low voltage environment, is provided. The voltage sensing circuit includes a current mirror having first and second terminals, a first switching element conf...	10/06/2011
20110242921	Systems And Methods Of Non-Volatile Memory Sensing Including Selective/Differential Threshold Voltage Features Systems and methods are disclosed for providing selective threshold voltage characteristics via use of MOS transistors having differential threshold voltages. In one exemplary embodiment, there is provided a metal oxide semiconductor device comprising a substrate of sem...	10/06/2011
20110235451	DYNAMIC RANDOM ACCESS MEMORY AND METHOD OF DRIVING DYNAMIC RANDOM ACCESS MEMORY A dynamic RAM which includes a first inverter, a second inverter, a sense amplifier, a first pair of switches, a pair of bit lines, and a dynamic RAM cell. The first inverter receives a first driving signal. A power end of the first inverter is coupled to a first voltag...	09/29/2011
20110235449	Dual Sensing Current Latched Sense Amplifier A sense amplifier and method thereof are provided. The sense amplifier includes first and second transistors coupled to first and second bit lines, respectively. The first and second transistors are configured to connect the first and second bit lines to a differential ...	09/29/2011
20110235450	CURRENT MODE SENSE AMPLIFIER WITH PASSIVE LOAD Memories, current mode sense amplifiers, and methods for operating the same are disclosed, including a current mode sense amplifier including cross-coupled p-channel transistors and a load circuit coupled to the cross-coupled p-channel transistors. The load circuit is c...	09/29/2011
20110235448	USING DIFFERENTIAL SIGNALS TO READ DATA ON A SINGLE-END PORT In some embodiments related to reading data in a memory cell, the data is driven to a local bit line, which drives a local sense amplifier. Depending on the logic level of the data in the memory cell and thus the local bit line, the local sense amplifier transfers the d...	09/29/2011
20110222361	NANO-SENSE AMPLIFIER A sense amplifier for a series of cells of a memory, including a writing stage comprising a CMOS inverter, the input of which is directly or indirectly connected to an input terminal of the sense amplifier, and the output of which is connected to an output terminal of t...	09/15/2011
20110216616	SEMICONDUCTOR MEMORY DEVICE A semiconductor memory device includes a first and second memory cell array region, a first and second sense amplifier region interposed between the first and second memory cell array regions, a first column selection region interposed between the first sense amplifier ...	09/08/2011
20110216601	CURRENT SINK SYSTEM BASED ON SAMPLE AND HOLD FOR SOURCE SIDE SENSING Source-side sensing techniques described herein determine the data value stored in a memory cell based on the difference in current between the read current from the source terminal of the memory cell and a sink current drawn from the read current. The sink current is d...	09/08/2011
20110216617	TECHNIQUES FOR SENSING A SEMICONDUCTOR MEMORY DEVICE Techniques for sensing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the technique(s) may be realized as a semiconductor memory device comprising a plurality of memory cells arranged in an array of rows and columns and data sense a...	09/08/2011
20110211409	Embedded Memory Databus Architecture A dynamic random access memory (DRAM) having pairs of bitlines, each pair being connected to a first bit line sense amplifier, wordlines crossing the bitlines pairs forming an array, charge storage cells connected to the bitlines, each having an enable input connected t...	09/01/2011
20110211407	SEMICONDUCTOR MEMORY DEVICE AND ASSOCIATED LOCAL SENSE AMPLIFIER A semiconductor memory device comprises a plurality of memory cells, a bit line sense amplifier, a local sense amplifier, and a sense amplifier. The memory cells are connected between a word line and a bit line pair, and the bit line sense amplifier is configured to amp...	09/01/2011
20110205821	Semiconductor device having sense amplifiers A semiconductor device includes a plurality of memory cells connected to a word line, sense amplifiers arranged correspondingly to the memory cells, and a sense-amplifier control circuit that activates the sense amplifiers in response to selection of the word line and t...	08/25/2011
20110205822	BITLINE SENSE AMPLIFIER, MEMORY CORE INCLUDING THE SAME AND METHOD OF SENSING CHARGE FROM A MEMORY CELL A bitline sense amplifier includes a pre-sensing unit and an amplification unit. The pre-sensing unit is connected to a first bitline and a second bitline, and is configured to perform a pre-sensing operation by controlling a voltage level of the second bitline based on...	08/25/2011
20110205820	Semiconductor device The semiconductor device comprises first and second memory cells, first and second bit lines connected to the first/second memory cells, first and second amplifiers connected to the second bit line, a local input/output line commonly connected to the first/second amplif...	08/25/2011
20110199844	Semiconductor Memory Device Suitable for Mounting on a Portable Terminal A semiconductor memory device for operating in synchronization with a clock is disclosed. The semiconductor includes a memory array having a plurality of memory cells arranged in rows and columns; and a control circuit performing a control, operation to effect row acces...	08/18/2011
20110199849	SENSE AMPLIFIER FOR CONTROLLING FLIP ERROR AND DRIVING METHOD THEREOF A sense amplifier and a driving method is described for resolving a flip failure occurrence where the voltage applied across the bit line is within an acceptable threshold range when the data is delivered to the data bus. The driving method includes disconnecting a bit ...	08/18/2011

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Class 365/207 - Differential sensing