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Pillow with retractable umbrella
A pillow assembly having a supporting assembly and a retractable umbrella assembly that is easily transportable and allows a user to support his/her head while covering their face from sunlight.
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| Application No. | Application Title | Issue Date |
| 20120127815 | SENSE AMPLIFIER AND METHOD OF SENSING DATA USING THE SAME Some embodiments regard a circuit comprising a pre-charge circuit and a latch circuit. The pre-charge circuit charges a voltage node to a pre-determined voltage level based on which the latch circuit generates a feedback signal to stop the pre-charge circuit from chargi... | 05/24/2012 |
| 20120106281 | SEMICONDUCTOR MEMORY DEVICES AND SEMICONDUCTOR MEMORY SYSTEMS A semiconductor memory device includes at least one memory cell block and at least one connection unit. The at least one memory cell block has a first region including at least one first memory cell connected to a first bit line, and a second region including at least o... | 05/03/2012 |
| 20120106277 | REFRESH OPERATION CONTROL CIRCUIT, SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME, AND REFRESH OPERATION CONTROL METHOD A semiconductor memory device includes a bank including a first cell region and a second cell region, an active signal generation unit configured to generate a first row active signal and a second row active signal having different activation periods from each other in ... | 05/03/2012 |
| 20120106280 | SELF-ADAPTIVE SENSING DESIGN A clock signal having a clock pulse width duration is received. A delay time is received. A first relationship and a second relationship between the clock pulse width duration and the delay time are determined. A new clock is generated that has a first new clock pulse w... | 05/03/2012 |
| 20120081949 | Active Bit Line Droop for Read Assist A static random access memory (SRAM) includes an SRAM cell to store a bit of data. A word line accesses the SRAM cell, which, responsively, during a read, drives either a bit line true (BLT) or a bit line complement (BLC) low. Both BLT and BLC are precharged to a supply... | 04/05/2012 |
| 20120081984 | THREE-DIMENSIONAL STACKED SEMICONDUCTOR INTEGRATED CIRCUIT Various embodiments of a three-dimensional, stacked semiconductor integrated circuit are disclosed. In one exemplary embodiment, the circuit may include a master slice, a plurality of slave slices, and a plurality of through-silicon vias for connecting the master slice ... | 04/05/2012 |
| 20120069684 | SEMICONDUCTOR INTEGRATED CIRCUIT According to one embodiment, a semiconductor integrated circuit includes a memory cell array includes data storage units which are arranged at intersections of word lines and bit lines and hold data, a reversing circuit which logically reverses held data stored in the d... | 03/22/2012 |
| 20120069622 | Sector Array Addressing for ECC Management An addressing scheme for non-volatile memory arrays having short circuit defects that manages the demand for error correction. The scheme generally avoids simultaneous active driving of the row line and column line of the selected cell during write. Instead, only a sing... | 03/22/2012 |
| 20120069636 | STATIC RANDOM ACCESS MEMORY (SRAM) HAVING BIT CELLS ACCESSIBLE BY SEPARATE READ AND WRITE PATHS A method is for reading a first bit cell of a static random access memory in which the static random access memory has a first plurality of bit cells including the first bit cell. Each bit cell of the first plurality of bit cells includes a cross coupled pair of inverte... | 03/22/2012 |
| 20120051126 | SEMICONDUCTOR MEMORY APPARATUS AND DATA READING METHOD THEREOF A semiconductor memory apparatus includes: a read current supply unit configured to supply a read current; a resistive memory cell configured to pass a current having a magnitude corresponding to a resistance value thereof in a data read mode; a voltage transfer unit co... | 03/01/2012 |
| 20120051156 | SEMICONDUCTOR MEMORY DEVICE A semiconductor memory device includes a pre-charger configured to pre-charge a first pair of differential bus lines SIO and SIOb to a target voltage level, an amplifier configured to amplify a signal loaded on the first pair of the differential bus lines SIO and SIOb b... | 03/01/2012 |
| 20120039141 | VOLTAGE CONTROL METHOD AND MEMORY DEVICE USING THE SAME A memory device is provided, which includes a plurality of global bit lines, a discharge line, a switching circuit configured to connect the plurality of global bit lines to the discharge line in response to a discharge enable signal, a first discharge circuit configure... | 02/16/2012 |
| 20120039142 | SCALEABLE LOOK-UP TABLE BASED MEMORY An integrated circuit having a logic element that includes an array of storage elements convertibly functioning as either a configuration random access memory (CRAM) or a static random access memory (SRAM) is provided. The logic element includes first and second pairs o... | 02/16/2012 |
| 20120033506 | SEMICONDUCTOR DEVICE A semiconductor device includes an internal circuit and an internal voltage generation circuit which generates an internal voltage stabilized with respect to a variation of the power supply voltage supplied from the outside and supplies the internal voltage to the inter... | 02/09/2012 |
| 20120033509 | Memory data reading and writing technique A novel circuit for reading data in solid state memory cells is presented. It can be used for any type of memory cell array but more specifically it is particularly suited for volatile memories like SRAM and DRAM. It is based on sensing the current in the ground line of... | 02/09/2012 |
| 20120033489 | MEMORY DEVICE, PRECHARGE CONTROLLING METHOD THEREOF, AND DEVICES HAVING THE SAME A pre-charge controlling method and device are provided. The pre-charge controlling method includes pre-charging a first global bit line with a first pre-charge voltage by using at least a first pre-charge circuit located between a plurality of sub arrays included in a ... | 02/09/2012 |
| 20120033517 | ADAPTIVE WRITE BIT LINE AND WORD LINE ADJUSTING MECHANISM FOR MEMORY A memory includes a capacitor coupled to a write bit line or a word line. An initializer is configured to initialize a voltage level at a first node between the capacitor and the write bit line or a word line. An initial level adjuster is configured to adjust a voltage ... | 02/09/2012 |
| 20120020169 | TWO-PORT SRAM WRITE TRACKING SCHEME A Static Random Access Memory (SRAM) includes at least two memory cells sharing a read bit line (RBL) and a write bit line (WBL). Each memory cell is coupled to a respective read word line (RWL) and a respective write word line (WWL). A write tracking control circuit is... | 01/26/2012 |
| 20120020149 | Semiconductor device A memory cell changes a potential of a bit line to a discharge potential from a precharge potential in correspondence with held data. A sense amplifier precharges a bit line by a precharge circuit, compares potential at a decision point linked with the potential of the ... | 01/26/2012 |
| 20120014197 | SEMICONDUCTOR DEVICE AND TEST METHOD THEREOF A semiconductor device includes a plurality of memory mats, each of which includes a plurality of word lines, a plurality of bit lines, a plurality of memory cells that are arranged at intersections of the word lines and the bit lines, and a plurality of dummy word line... | 01/19/2012 |
| 20120014158 | MEMORY DEVICES A memory device includes an array of transistors, a plurality of bit lines, and a plurality of source lines. The transistors include gate, drain and source terminals. The gate terminals are electrically coupled to word lines. The plurality of bit lines connect a power s... | 01/19/2012 |
| 20120014196 | PROCESSOR INSTRUCTION CACHE WITH DUAL-READ MODES A processor including a cache memory, a decoder, a precharge circuit, a control module, and an amplifier module. The decoder generates a first word line signal to access first instructions stored in a first word line, and (ii) generates a second word line signal to acce... | 01/19/2012 |
| 20120008443 | IMPLEMENTING SMART SWITCHED DECOUPLING CAPACITORS TO EFFICIENTLY REDUCE POWER SUPPLY NOISE A method and circuit are provided for implementing smart switched decoupling capacitors to efficiently reduce power supply noise in a logic circuit, and a design structure on which the subject circuit resides. The logic circuit includes a logic macro, a high-current eve... | 01/12/2012 |
| 20120008446 | PRECHARGING CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME A semiconductor memory device includes a write driver for transmitting data loaded on a global line to a local line pair, a read driver for transmitting data loaded on the local line pair to the global line, a core region for storing data loaded on the local line pair o... | 01/12/2012 |
| 20120008445 | DUAL BIT LINE PRECHARGE ARCHITECTURE AND METHOD FOR LOW POWER DYNAMIC RANDOM ACCESS MEMORY (DRAM) INTEGRATED CIRCUIT DEVICES AND DEVICES INCORPORATING EMBEDDED DRAM A dual bit line precharge architecture and method for low power DRAM which provides the low operating voltage of a non-half supply voltage (VCC/2) precharge with the low memory array current consumption and low memory array noise spike of VCC/2 precharge techniques. The... | 01/12/2012 |
| 20120008368 | Semiconductor device having single-ended sensing amplifier A semiconductor device includes a bit line, a memory cell coupled to the bit line, the memory cell being configured such that a current flowing there the memory cell is varied in accordance with information stored M the memory cell, a first transistor coupled at a contr... | 01/12/2012 |
| 20120008444 | DUAL BIT LINE PRECHARGE ARCHITECTURE AND METHOD FOR LOW POWER DYNAMIC RANDOM ACCESS MEMORY (DRAM) INTEGRATED CIRCUIT DEVICES AND DEVICES INCORPORATING EMBEDDED DRAM A dual bit line precharge architecture and method for low power DRAM which provides the low operating voltage of a non-half supply voltage (VCC/2) precharge with the low memory array current consumption and low memory array noise spike of VCC/2 precharge techniques. The... | 01/12/2012 |
| 20120002496 | Circuit and method for eliminating bit line leakage current in random access memory devices A method for eliminating bit line leakage current of a memory cell in random access memory devices comprises the steps of: periodically activating a pre-charge equalization circuit, which provides a pre-charge voltage to a pair of complementary bit lines of a memory cel... | 01/05/2012 |
| 20120002497 | Circuit and method for controlling standby leakage current in random access memory devices A method for controlling standby current coming from bit line leakage in random access memory devices comprises the steps of: continuously deactivating a pre-charge equalization circuit providing a pre-charge voltage to a pair of complementary bit lines of a memory cell... | 01/05/2012 |
| 20110317505 | INTERNAL BYPASSING OF MEMORY ARRAY DEVICES An output control circuit for a memory array includes a latched output node precharged to a first logic state prior to both a read and write operation; first logic that couples memory cell data from a memory read path to the output node during the read operation, the fi... | 12/29/2011 |
| 20110317506 | Method for Asymmetric Sense Amplifier Methods for determining the state of memory cells include using an asymmetric sense amplifier. The methods include sensing the voltages on bit line (BL) and bit line bar (BLB) signals by coupling the BL to a first output node of an imbalanced cross-coupled latch (ICL), ... | 12/29/2011 |
| 20110317508 | MEMORY WRITE OPERATION METHODS AND CIRCUITS In some embodiments, write wordline boost may be obtained from wordline driver boost and/or from bit line access transistor boost.... | 12/29/2011 |
| 20110317476 | Bit-by-Bit Write Assist for Solid-State Memory A solid-state memory in which write assist circuitry is implemented within each memory cell. Each memory cell includes a storage element, such as a pair of cross-coupled inverters, that is connected in series with a pair of power switch transistors between a power suppl... | 12/29/2011 |
| 20110305098 | SEMICONDUCTOR MEMORY DEVICE WITH SENSE AMPLIFIER AND BITLINE ISOLATION A semiconductor memory device, including: a memory cell connected to a first bitline and associated with a second bitline; a sense amplifier, including a first input/output node and a second input/output node; and an isolator connected to the bitlines and to the input/o... | 12/15/2011 |
| 20110305099 | HIERARCHICAL BUFFERED SEGMENTED BIT-LINES BASED SRAM A semiconductor memory device is disclosed. In one aspect, the device includes memory blocks with memory cells connected to a local bit-line, each local bit-line being connectable to a global bit-line for memory readout. There are also pre-charging circuitry for pre-cha... | 12/15/2011 |
| 20110299349 | Margin Testing of Static Random Access Memory Cells A static random access memory (SRAM) and method of evaluating the same for cell stability, write margin, and read current margin. The memory is constructed so that bit line precharge can be disabled, and so that complementary bit lines for each column of cells can float... | 12/08/2011 |
| 20110299350 | PRECHARGE CONTROL CIRCUIT AND INTEGRATED CIRCUIT INCLUDING THE SAME A precharge control circuit includes a precharge voltage supply unit for generating a precharge voltage according to a voltage level of a precharge control signal, a voltage generator for generating an operating voltage for controlling the voltage level of the precharge... | 12/08/2011 |
| 20110292749 | NON-VOLATILE MEMORY DEVICE A non-volatile memory device includes a plurality of mats, each of which includes a unit cell in an intersection area between each of a plurality of word lines and each of a plurality of bit lines such that a read or write operation of data is achieved in each mat, a co... | 12/01/2011 |
| 20110292715 | SEMICONDUCTOR MEMORY DEVICE A semiconductor memory device includes a memory cell array in which a plurality of memory cells is aligned in a matrix shape, each memory cell including a two-terminal memory element and a transistor for selection connected in series; a first voltage applying circuit th... | 12/01/2011 |
| 20110292748 | IMPLEMENTING LOW POWER DATA PREDICTING LOCAL EVALUATION FOR DOUBLE PUMPED ARRAYS A method and static random access memory (SRAM) circuit for implementing low power data predicting local evaluation for double pumped arrays, and a design structure on which the subject circuit reside are provided. A novel variation of a domino read local evaluation cir... | 12/01/2011 |
