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| Application No. | Application Title | Issue Date |
| 20120127797 | SYSTEM AND METHOD FOR TESTING FOR DEFECTS IN A SEMICONDUCTOR MEMORY ARRAY A system and method for testing semiconductor memory devices includes a variable voltage input to a memory cell control gate. The voltage to the control gate can be varied from a voltage level used for normal memory cell operation, such as a read operation, to a voltage... | 05/24/2012 |
| 20120127814 | SEMICONDUCTOR DEVICE PERFORMING STRESS TEST A semiconductor device includes a memory cell array that is divided into a plurality of memory cell mats by a plurality of sense amplifier arrays. Each of the plurality of memory cell mats includes a plurality of word lines and a test circuit for performing a test contr... | 05/24/2012 |
| 20120131399 | APPARATUS AND METHODS FOR TESTING MEMORY CELLS Apparatus and methods are provided for concurrently selecting multiple arrays of memory cells when accessing a memory element. A memory element includes a first array of one or more memory cells coupled to a first bit line node, a second array of one or more memory cell... | 05/24/2012 |
| 20120106279 | SEMICONDUCTOR MEMORY APPARATUS, MEMORY SYSTEM, AND PROGRAMMING METHOD THEREOF Various embodiments of a semiconductor memory apparatus are disclosed. In one exemplary embodiment, the semiconductor memory apparatus includes a core block configured to receive and store external input data, a control unit configured to activate a control signal in re... | 05/03/2012 |
| 20120106227 | INTEGRATED CIRCUIT An integrated circuit includes a normal data storage unit configured to store normal data and output the stored normal data in response to a write command, a read command, and an address signal in a normal operation mode, a test data storage unit configured to store the... | 05/03/2012 |
| 20120069689 | BUILT-IN SELF REPAIR FOR MEMORY A method for repairing a memory includes running a built-in self-test of the memory to find faulty bits. A first repair result using a redundant row block is calculated. A second repair result using a redundant column block is calculated. The first repair result and the... | 03/22/2012 |
| 20120072790 | On-Chip Memory Testing An integrated circuit is described that has a substrate with a memory array with dedicated support hardware formed on the substrate. An access wrapper circuit is coupled to address and data lines of the memory array and to control lines of the dedicated support hardware... | 03/22/2012 |
| 20120072792 | MEMORY TESTER AND COMPILER WHICH MATCHES A TEST PROGRAM According to one embodiment, a memory tester is provided. The memory tester has first and second operation registers, a first selector, and first and second burst address generating circuits. The first operation register stores a first operation variable. The second ope... | 03/22/2012 |
| 20120044755 | System and Method of Reference Cell Testing In a particular embodiment, a method of testing a reference cell in a memory array includes coupling a first reference cell of a first reference cell pair of the memory array to a first input of a first sense amplifier of the memory array. The method also includes provi... | 02/23/2012 |
| 20120033490 | Generating a Non-Reversible State at a Bitcell Having a First Magnetic Tunnel Junction and a Second Magnetic Tunnel Junction A method of generating a non-reversible state at a bitcell having a first magnetic tunnel junction (MTJ) and a second MTJ includes applying a program voltage to the first MTJ of the bitcell without applying the program voltage to the second MTJ of the bitcell. A memory ... | 02/09/2012 |
| 20120033516 | WORD LINE DRIVING CIRCUIT, SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME, AND METHOD FOR TESTING THE SEMICONDUCTOR MEMORY DEVICE A semiconductor memory device in accordance with the present invention is able to facilitate detecting whether a word line fails or not by floating the word line. The semiconductor memory device includes a word line driver, and a floating controller. The word line drive... | 02/09/2012 |
| 20120026809 | MULTI-BIT TEST CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS A multi-bit test circuit for a semiconductor memory is configured to cause an active command to activate active signals. At least two active signals are respectively inputted to a plurality of banks at different timings in a multi-bit test mode.... | 02/02/2012 |
| 20120026817 | Low Cost Testing and Sorting of Integrated Circuits Methods of testing and sorting integrated circuits in clusters are disclosed. Each cluster has power and data terminals connected to common power and data busses providing a common power supply. Each integrated circuit has a first non-volatile memory storing an activati... | 02/02/2012 |
| 20120020164 | TEST METHOD FOR SCREENING MANUFACTURING DEFECTS IN A MEMORY ARRAY A method of screening manufacturing defects at a memory array may include programming a background pattern of physically inverse data along conductive lines extending in a first direction. The programming may include providing a program conductive line with a high value... | 01/26/2012 |
| 20120014197 | SEMICONDUCTOR DEVICE AND TEST METHOD THEREOF A semiconductor device includes a plurality of memory mats, each of which includes a plurality of word lines, a plurality of bit lines, a plurality of memory cells that are arranged at intersections of the word lines and the bit lines, and a plurality of dummy word line... | 01/19/2012 |
| 20120008441 | SEMICONDUCTOR MEMORY DEVICE AND TEST METHOD THEREOF A semiconductor memory device includes a repair control signal generation unit configured to compare a repair target address programmed corresponding to a repair target memory cell with an external address, and generate a repair control signal. an address decoding unit ... | 01/12/2012 |
| 20120008434 | SEMICONDUCTOR SYSTEM AND DEVICE, AND METHOD FOR CONTROLLING REFRESH OPERATION OF STACKED CHIPS A system for controlling a refresh operation of a plurality of stacked semiconductor chips includes a first semiconductor configured to output a refresh signal for performing a refresh operation, and a semiconductor chip discrimination signal, and a plurality of second ... | 01/12/2012 |
| 20120008442 | SEMICONDUCTOR DEVICE AND METHOD OF TESTING THE SAME A semiconductor device according to an aspect of the present disclosure includes a test mode signal generator configured to generate a test mode setup signal, and a controller configured to set a separated test operation in response to the test mode setup signal.... | 01/12/2012 |
| 20120002491 | TEST SIGNAL GENERATING DEVICE, SEMICONDUCTOR MEMORY APPARATUS USING THE SAME AND MULTI-BIT TEST METHOD THEREOF A semiconductor memory apparatus includes a multi-bit test signal generating device configured to receive an address signal and generate a multi-bit test signal based on the address signal when a multi-bit test write operation is performed.... | 01/05/2012 |
| 20120002494 | TEST MODE CONTROL CIRCUIT IN SEMICONDUCTOR MEMORY DEVICE AND TEST MODE ENTERING METHOD THEREOF A test mode control circuit is provided to strictly allow entry into a test mode or prevent a boot failure from occurring during a boot operation for a built-in parallel bit test. The test mode control circuit includes a latch, a real entry signal detector, an entry det... | 01/05/2012 |
| 20120002495 | MEMORY SYSTEM, MEMORY TEST SYSTEM AND METHOD OF TESTING MEMORY SYSTEM AND MEMORY TEST SYSTEM A memory test system is disclosed. The memory system includes a memory device, a tester generating a clock signal and a test signal for testing the memory device, and an optical splitting module. The optical splitting module comprises an electrical-optical signal conver... | 01/05/2012 |
| 20110310686 | Method and Circuit for Configuring Memory Core Integrated Circuit Dies with Memory Interface Integrated Circuit Dies A memory device comprises a first and second integrated circuit dies. The first integrated circuit die comprises a memory core as well as a first interface circuit. The first interface circuit permits full access to the memory cells (e.g., reading, writing, activating, ... | 12/22/2011 |
| 20110310685 | MEMORY MODULE INCLUDING PARALLEL TEST APPARATUS A memory module including a plurality of ranks. Each of the ranks includes a parallel test apparatus for simultaneous testing and a parallel test control unit. In response to a parallel test mode control signal, the parallel test apparatus generates first parity data fo... | 12/22/2011 |
| 20110299349 | Margin Testing of Static Random Access Memory Cells A static random access memory (SRAM) and method of evaluating the same for cell stability, write margin, and read current margin. The memory is constructed so that bit line precharge can be disabled, and so that complementary bit lines for each column of cells can float... | 12/08/2011 |
| 20110292745 | DATA TRANSMISSION DEVICE A data transmission device in a semiconductor memory apparatus receives input data via a local data input/output line and output s the input data on a plurality of global data input/output lines. The data transmission device includes a write data generation block config... | 12/01/2011 |
| 20110292741 | Memory Apparatus and Associated Method A memory apparatus includes a plurality of first bit columns for constructing a common memory space and at least one reserve second bit column. A column address of a damaged first bit column is recorded as a predetermined column address. When a byte column is accessed, ... | 12/01/2011 |
| 20110280092 | Multi-Bank Read/Write To Reduce Test-Time In Memories Apparatuses and methods for multi-bank read/write architecture to reduce test time in memory devices are disclosed. A memory device can include a memory cell array including a plurality of memory banks. A bank decoding circuit can include logic configured to simultaneou... | 11/17/2011 |
| 20110280090 | Semiconductor device and test method thereof For example, to include plural data input/output terminals and a strobe terminal that are electrically connected in common by a test probe, a command address terminal that is connected to a test probe, and an output control circuit that performs a selecting operation of... | 11/17/2011 |
| 20110280091 | MEMORY REPAIR SYSTEMS AND METHODS FOR A MEMORY HAVING REDUNDANT MEMORY Memories, memory repair logic, and methods for repairing a memory having redundant memory are disclosed. One such memory includes programmable elements associated with respective redundant memory configured to have memory addresses mapped thereto, the programmable eleme... | 11/17/2011 |
| 20110273924 | SEMICONDUCTOR MEMORY DEVICE A semiconductor memory device is provided which includes a voltage detecting unit configured to compare a target voltage level with a fed-back internal voltage to output a detection signal in a normal mode, a driving unit configured to selectively drive an internal volt... | 11/10/2011 |
| 20110273946 | UNIVERSAL TEST STRUCTURES BASED SRAM ON-CHIP PARAMETRIC TEST MODULE AND METHODS OF OPERATING AND TESTING An integrated circuit on-chip parametric (OCP) test structure includes a static random access memory (SRAM) universal test structure (UTS) having UTS ports and an OCP controller configured to determine first and second UTS ports of the SRAM UTS for independent connectio... | 11/10/2011 |
| 20110267908 | REPAIR CIRCUIT AND REPAIR METHOD OF SEMICONDUCTOR MEMORY APPARATUS A repair circuit of a semiconductor memory apparatus includes a repair address detection circuit that determines the occurrence of a failure in a memory block based on a plurality of test data signals outputted from the memory block, and stores an address corresponding ... | 11/03/2011 |
| 20110267906 | Measuring SDRAM Control Signal Timing Measuring control signal timing for synchronous dynamic random access memory (‘SDRAM’), including combining into a trigger signal for an oscilloscope display control signals of an SDRAM under test, the control signals derived only from a single type of memory operat... | 11/03/2011 |
| 20110267875 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR TESTING THE SAME A semiconductor memory device includes a memory cell array configured to include a plurality of memory cells, a plurality of bit lines respectively coupled to the plurality of memory cells, a first power-supply voltage supplying circuit configured to provide a first pow... | 11/03/2011 |
| 20110267911 | SEMICONDUCTOR MEMORY APPARATUS A semiconductor memory apparatus includes: a line calibration unit configured to selectively output one signal from the group of code signals for calibrating termination resistance values and test mode signals for testing a chip of the semiconductor memory apparatus to ... | 11/03/2011 |
| 20110255340 | Nonvolatile semiconductor memory and method for testing the same A nonvolatile semiconductor memory, includes a nonvolatile memory array, a voltage generator circuit that generates a drive voltage which changes depending on a supply voltage and a code, a control circuit that applies the generated drive voltage to the nonvolatile memo... | 10/20/2011 |
| 20110255357 | DYNAMIC RANDOM ACCESS MEMORY (DRAM) REFRESH A method for refreshing a Dynamic Random Access Memory (DRAM) includes performing a refresh on at least a portion of the DRAM at a first refresh rate, and performing a refresh on a second portion of the DRAM at a second refresh rate. The second portion includes one or m... | 10/20/2011 |
| 20110249510 | EMBEDDED STORAGE APPARATUS AND TEST METHOD THEREOF An embedded storage apparatus including a control unit, a storage unit, and a signal processing and measurement unit is provided. The control unit outputs a plurality of signals, wherein the signals include a mode selection signal and a plurality of control signals. The... | 10/13/2011 |
| 20110242919 | Precharge Voltage Supplying Circuit A precharge voltage supplying circuit comprises a transistor operating in response to a control signal, wherein the transistor is connected between a first node to which an internal voltage is supplied and a second node to which a precharge voltage is supplied, and a re... | 10/06/2011 |
| 20110242918 | GLOBAL LINE SHARING CIRCUIT OF SEMICONDUCTOR MEMORY DEVICE A global line sharing circuit of a semiconductor memory device includes: a ZQ calibration unit configured to adjust an impedance of a DQ output driver; a test unit configured to control a test operation; and a shared global line coupled to and used in common by the ZQ c... | 10/06/2011 |
