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| Application No. | Application Title | Issue Date |
| 20120127810 | SEMICONDUCTOR MEMORY DEVICE AND ACCESS METHOD THEREOF Example embodiments provide a semiconductor memory device that may include: a cell array arranged in pluralities of rows and columns; and a sense amplifier conducting writing and reading operations to the cell array in response to writing and reading commands in corresp... | 05/24/2012 |
| 20120127809 | PRECHARGE SIGNAL GENERATION CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS A precharge signal generation circuit of a semiconductor memory apparatus may comprise a read/write precharge command generation section configured to delay a precharge command by a first delay time set in response to a control signal to generate one of a read precharge... | 05/24/2012 |
| 20120106263 | INPUT/OUTPUT CIRCUIT AND METHOD OF SEMICONDUCTOR APPARATUS AND SYSTEM WITH THE SAME A system includes a controller which is capable of operating at one of a first speed and a second speed slower than the first speed; a semiconductor memory apparatus operating at the first speed; and an input/output device which is connected between the semiconductor me... | 05/03/2012 |
| 20120106273 | SEMICONDUCTOR MEMORY APPARATUS Various embodiments of a semiconductor memory apparatus are disclosed. In one exemplary embodiment, the semiconductor memory apparatus may include: a column control signal generator configured to generate a column control signal for a pair of bit lines corresponding to ... | 05/03/2012 |
| 20120106276 | DATA STROBE SIGNAL GENERATION CIRCUIT A data strobe signal generation circuit includes: an enable signal generation unit configured to decode a test signal and generate an enable signal; an internal clock generation unit configured to generate a rising clock signal and a falling clock signal in response to ... | 05/03/2012 |
| 20120106274 | SEMICONDUCTOR MEMORY APPARATUS A semiconductor memory apparatus includes a data input enable signal generation block configured to sequentially delay a data strobe signal to generate a first delayed data strobe signal, a second delayed data strobe signal, a third delayed data strobe signal and a four... | 05/03/2012 |
| 20120106275 | RINGBACK CIRCUIT FOR SEMICONDUCTOR MEMORY DEVICE A circuit for a semiconductor memory device includes: a filtering control signal generation unit configured to synchronize a seed signal activated in a pre-amble period of a data strobe signal with the data strobe signal and sequentially generate a plurality of filterin... | 05/03/2012 |
| 20120110400 | Method and Apparatus for Performing Memory Interface Calibration A universal memory interface on an integrated circuit includes an external memory interface unit operable to perform data rate conversion for a data signal between a first rate associated with the integrated circuit and a second rate associated with a memory system. The... | 05/03/2012 |
| 20120081981 | NONVOLATILE MEMORY APPARATUS WITH CHANGEABLE OPERATION SPEED AND RELATED SIGNAL CONTROL METHOD Various embodiments of a nonvolatile memory apparatus configured to operate in a first operation mode and a second operation mode are disclosed. In one exemplary embodiment, the apparatus may include: a controller configured to enable complementary signal input/output b... | 04/05/2012 |
| 20120069687 | Semiconductor memory device and read wait time adjustment method thereof, memory system, and semiconductor device A controller includes a set of first terminals to be coupled to a device that is under control of the controller, and a control circuit configured to generate and output onto the set of first terminals synchronous mode information including a selected one of selection a... | 03/22/2012 |
| 20120054562 | SEMICONDUCTOR MEMORY DEVICE A semiconductor memory device having a bank including a redundancy cell block and a plurality of normal cell blocks includes a plurality of normal data inputting/outputting units configured to respectively input/output data from the normal cell blocks in response to a f... | 03/01/2012 |
| 20120042220 | LOW-COST DESIGN FOR REGISTER FILE TESTABILITY A self-test module for use in an electronic device includes a test controller and a memory. The memory is configured to receive test vectors from the test controller. A comparator is configured to receive the test data from the memory via an output data path. A strobing... | 02/16/2012 |
| 20120039139 | Memory Systems and Methods for Dividing Physical Memory Locations Into Temporal Memory Locations Described are memory modules that support dynamic point-to-point extensibility using fixed-width memory die. The memory modules include data-width translators that allow the modules to vary the effective width of their external memory interfaces without varying the widt... | 02/16/2012 |
| 20120039138 | ASYNCHRONOUS PIPELINED MEMORY ACCESS A plurality of control signals are asserted within an asynchronous integrated circuit memory device in response to each transition of a memory access initiation signal to effect pipelined memory access operations.... | 02/16/2012 |
| 20120033514 | STROBE-OFFSET CONTROL CIRCUIT A method of operation in a memory controller is disclosed. The method includes receiving a strobe signal having a first phase relationship with respect to first data propagating on a first data line, and a second phase relationship with respect to second data propagatin... | 02/09/2012 |
| 20120033513 | DISTRIBUTED WRITE DATA DRIVERS FOR BURST ACCESS MEMORIES An address strobe latches a first address. A burst cycle increments the address internally with additional address strobes. A new memory address is only required at the beginning of each burst access. Read commands are issued once per burst access eliminating toggling R... | 02/09/2012 |
| 20120026806 | DATA INPUT CIRCUIT A data input circuit includes a valid strobe signal generation circuit and a data strobe signal counter. The valid strobe signal generation circuit is configured to remove a pulse of an internal strobe signal generated and generate a valid strobe signal. The pulse may h... | 02/02/2012 |
| 20120020171 | MEMORY SYSTEM WITH DELAY LOCKED LOOP (DLL) BYPASS CONTROL A memory system with delay locked loop (DLL) bypass control including a method for accessing memory that includes receiving a memory read command at a memory device. The memory device is configured to operate in a DLL off-mode to bypass a DLL clock as input to generatin... | 01/26/2012 |
| 20120020172 | DATA STROBE SIGNAL GENERATING DEVICE AND A SEMICONDUCTOR MEMORY APPARATUS USING THE SAME A data strobe signal generating device includes a preamble controller configured to generate a preamble signal enabled in synchronization with a first dock signal and disabled in synchronization with a second clock signal after an output enable signal is enabled, and a ... | 01/26/2012 |
| 20120008426 | HIGH SPEED DRAM ARCHITECTURE WITH UNIFORM ACCESS LATENCY A Dynamic Random Access Memory (DRAM) performs read, write, and refresh operations. The DRAM includes a plurality of sub-arrays, each having a plurality of memory cells, each of which is coupled with a complementary bit line pair and a word line. The DRAM further includ... | 01/12/2012 |
| 20110317502 | CONTROL OF INPUTS TO A MEMORY DEVICE A memory device includes a command decoder and control interface logic. One or more external inputs, such as row and column address strobes, communicate with the command decoder through the control interface logic. A control signal is also in communication with the cont... | 12/29/2011 |
| 20110299347 | DYNAMIC DETECTION OF A STROBE SIGNAL WITHIN AN INTEGRATED CIRCUIT A method of processing a strobe signal can include oversampling a strobe signal received from a source synchronous device and determining an amount of time between sending a read request to the source synchronous device and detecting a first pulse of the strobe signal a... | 12/08/2011 |
| 20110299348 | SEMICONDUCTOR MEMORY DEVICE AND INTEGRATED CIRCUIT A semiconductor memory device includes a write control signal generating circuit and a write enable signal generating unit. The write control signal generating circuit is configured to generate a write control signal activated during a time period from an input time poi... | 12/08/2011 |
| 20110299346 | APPARATUS FOR SOURCE-SYNCHRONOUS INFORMATION TRANSFER AND ASSOCIATED METHODS An apparatus includes an interface circuit coupled to an electronic device. The interface circuit provides source synchronous communication with the electronic device using a strobe signal. The interface circuit is configured to gate the strobe signal in order to succes... | 12/08/2011 |
| 20110292739 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME A semiconductor memory device includes a data alignment unit configured to align data, which are sequentially inputted, in response to a data strobe signal, a latching operation control unit configured to receive the data strobe signal, and generate a latching control s... | 12/01/2011 |
| 20110280090 | Semiconductor device and test method thereof For example, to include plural data input/output terminals and a strobe terminal that are electrically connected in common by a test probe, a command address terminal that is connected to a test probe, and an output control circuit that performs a selecting operation of... | 11/17/2011 |
| 20110267898 | SEMICONDUCTOR MEMORY APPARATUS A semiconductor memory apparatus includes a clock transmission unit configured to selectively output a data strobe clock signal or a phase correction clock signal based on an operation mode, and a data latch unit configured to latch a plurality of data signals under a c... | 11/03/2011 |
| 20110267907 | SEMICONDUCTOR MEMORY DEVICE, SEMICONDUCTOR SYSTEM INCLUDING THE SEMICONDUCTOR MEMORY DEVICE, AND METHOD FOR OPERATING THE SEMICONDUCTOR MEMORY DEVICE A semiconductor memory device includes a first data input/output unit configured to receive a normal training data, whose data window is scanned based on an edge of a source clock, in response to a training input command, and output a data in a state where an edge of th... | 11/03/2011 |
| 20110261636 | COMMON MEMORY DEVICE FOR VARIABLE DEVICE WIDTH AND SCALABLE PRE-FETCH AND PAGE SIZE Embodiments of the invention are generally directed to systems, methods, and apparatuses for a common memory device for variable device width and scalable pre-fetch and page size. In some embodiments, a common memory device (such as a DRAM) can operate in any of a numbe... | 10/27/2011 |
| 20110255354 | SEMICONDUCTOR INTEGRATED CIRCUIT Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including a data transmitting circuit that transmits data in parallel through a plurality of signal lines and a data receiving circuit that receives the data. The da... | 10/20/2011 |
| 20110249514 | METHODS AND APPARATUS FOR STROBE SIGNALING AND EDGE DETECTION THEREOF A data system component having a state machine circuit and receivers that utilize high and low threshold signals permits accurate detection of strobe signal pattern edges such as those for preamble, burst and post-amble conditions in the strobe signal. The state machine... | 10/13/2011 |
| 20110249520 | DATA STROBE SIGNAL OUTPUT DRIVER FOR A SEMICONDUCTOR MEMORY APPARATUS A data strobe signal output driver includes a trigger block, a predriver block, and a main driver block. The trigger block is configured to receive a first signal, a second signal, a first clock and a second clock, and to output a predrive signal based thereon. The pred... | 10/13/2011 |
| 20110249521 | Semiconductor device A semiconductor device includes: a clock generator generating a first internal clock signal based on an external clock signal; a clock divider generating second and third internal clock signals based on the first internal clock signal and including an edge adjustor adju... | 10/13/2011 |
| 20110242909 | SEMICONDUCTOR DEVICE AND SYSTEM A system includes a data transmitting device and a data receiving device. The data transmitting device includes a data strobe signal generation unit configured to generate first and second data strobe signals in response to an output enable signal, and a data output uni... | 10/06/2011 |
| 20110242908 | COMMAND DECODER AND A SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME A command decoder includes a snoop read control signal generation unit that generates a snoop read control signal from a internal chip select signal according to a level of a transmission mode control signal, and an internal snoop read command generation unit that gener... | 10/06/2011 |
| 20110242910 | DATA STROBE CLOCK BUFFER IN SEMICONDUCTOR MEMORY APPARATUS, METHOD OF CONTROLLING THE SAME, AND SEMICONDUCTOR APPARATUS HAVING THE SAME A data strobe clock buffer of a semiconductor memory apparatus includes a buffering block configured to buffer an external data strobe clock signal in response to a buffer enable signal to generate an internal data strobe clock signal, a timing discriminating block conf... | 10/06/2011 |
| 20110242907 | SEMICONDUCTOR MEMORY APPARATUS AND READ/WRITE CONTROL METHOD THEREOF A semiconductor memory apparatus includes: a read/write control unit configured to generate a write control signal and a read control signal using internal signals generated through separate signal paths in response to a write command and a read command respectively; an... | 10/06/2011 |
| 20110235426 | FLASH MEMORY SYSTEM HAVING A PLURALITY OF SERIALLY CONNECTED DEVICES A semiconductor memory device and system are disclosed. The memory device includes a memory, a plurality of inputs, and a device identification register for storing register bits that distinguish the memory device from other possible memory devices. Circuitry for compar... | 09/29/2011 |
| 20110235446 | WRITE STROBE GENERATION FOR A MEMORY INTERFACE CONTROLLER A memory controller includes a circuit to generate a strobe signal for write operations to a DDR SDRAM. The circuit efficiently generates a glitch free strobe signal for a group of data lines. In one implementation, the memory controller includes a write data generation... | 09/29/2011 |
| 20110228619 | MEMORY CONTROL APPARATUS AND MASK TIMING ADJUSTING METHOD A disclosed synchronous memory control apparatus for enabling reception of data read from a memory circuit in synchronism with a strobe signal from the memory circuit includes a mask circuit masking the strobe signal using a mask signal; a timing measuring circuit delay... | 09/22/2011 |
