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An armor with rollers is provided that enables a user to move in all positions by rolling on a hard and smooth surface while constantly varying his bearing points on the ground.
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| Application No. | Application Title | Issue Date |
| 20120051158 | VOLTAGE SIGNALS SWITCHING CIRCUIT A switching circuit comprises a control and bias stage configured for receiving a first input voltage signal, a second input voltage signal and a selection signal and for generating therefrom a first bulk bias signal substantially equal to the first input voltage signal... | 03/01/2012 |
| 20120033508 | LEVEL SHIFTER FOR USE WITH MEMORY ARRAYS In a first aspect, a level shifter circuit for use in a memory array is provided that includes (1) a first voltage domain powered by a first voltage; (2) a second voltage domain powered by a second voltage; (3) level shifter circuitry that converts an input signal from ... | 02/09/2012 |
| 20120026802 | MANAGED HYBRID MEMORY WITH ADAPTIVE POWER SUPPLY Subject matter disclosed herein relates to a memory device, and more particularly to a managed hybrid memory that includes a power supply.... | 02/02/2012 |
| 20120014193 | CHARGE PUMP CIRCUIT, NONVOLATILE MEMORY, DATA PROCESSING APPARATUS, AND MICROCOMPUTER APPLICATION SYSTEM Improvement technology of a charge pump circuit is provided for avoiding device destruction due to electrification of an intermediate node of plural capacitors coupled in series to form one step-up capacitor, and avoiding reduction of pump efficiency due to leakage curr... | 01/19/2012 |
| 20120014192 | Two stage voltage level shifting A voltage level shifter for shifting an output signal from a first voltage level to a second voltage level and then to a further boosted second voltage level is disclosed. The voltage level shifter comprises: an input for receiving an input signal; an output for outputt... | 01/19/2012 |
| 20120008427 | Semiconductor Memory Device To Reduce Off-Current In Standby Mode A semiconductor memory device capable of reducing off-current in a standby mode is provided. The semiconductor memory device includes an enable signal generating unit configured to receive a plurality of address decoding signals and generate a first enable signal to sel... | 01/12/2012 |
| 20110317499 | SPLIT VOLTAGE LEVEL RESTORE AND EVALUATE CLOCK SIGNALS FOR MEMORY ADDRESS DECODING A method of implementing voltage level shifting for a memory device includes coupling one or more evaluation clock signals to a memory address decode circuit, the one or more evaluation clock signals operating at a first voltage supply level; and coupling a restore cloc... | 12/29/2011 |
| 20110286289 | SYSTEM AND METHOD OF SELECTIVELY VARYING SUPPLY VOLTAGE WITHOUT LEVEL SHIFTING DATA SIGNALS An electronic system implements a plurality of voltage domains, at least one of which has a selectively variable supply voltage, without requiring the use of a large number of level shifters (e.g., for each data and/or address line). The supply voltage for a first domai... | 11/24/2011 |
| 20110286291 | SEMICONDUCTOR MEMORY DEVICE COMPRISING A PLURALITY OF STATIC MEMORY CELLS A driver power supply circuit stepping down a power supply voltage is arranged at a power supply node of a word line driver. The driver power supply circuit includes a non-silicide resistance element of N+ doped polycrystalline silicon, and a pull-down circuit lowering ... | 11/24/2011 |
| 20110280088 | SINGLE SUPPLY SUB VDD BITLINE PRECHARGE SRAM AND METHOD FOR LEVEL SHIFTING A reduced bitline precharge level has been found to increase the SRAM Beta ratio, thus improving the stability margin. The precharge level is also supplied to Sense amplifier, write driver, and source voltages for control signals. In the sense amplifier, the lower prech... | 11/17/2011 |
| 20110273940 | LEVEL SHIFTING CIRCUIT A level shifting circuit having an input and an output where the level shifting circuit is configured to receive a logical high level having a first voltage level at the input and to output a logical high level having a second voltage level at the output where the secon... | 11/10/2011 |
| 20110267900 | SEMICONDUCTOR MEMORY DEVICE A semiconductor memory device includes a pad, an impedance calibration circuit configured to provide a first code value corresponding to an impedance value coupled to the pad, a PVT sensing control circuit configured to provide a second code value corresponding to a PVT... | 11/03/2011 |
| 20110267869 | CIRCUIT FOR VERIFYING THE WRITE ENABLE OF A ONE TIME PROGRAMMABLE MEMORY A memory system including a one time programmable (OTP) memory is provided. The memory system further includes a write enable verification circuit including an asymmetric inverter stage and a symmetric inverter stage coupled at a node. The write enable verification circ... | 11/03/2011 |
| 20110267902 | Semiconductor device A semiconductor device includes a drive circuit that outputs a drive signal to drive an external device; a voltage output circuit that outputs a first voltage and a second voltage that is larger than the first voltage; a selector that, when supplying a power supply volt... | 11/03/2011 |
| 20110261631 | SEMICONDUCTOR DEVICE AND DATA PROCESSING SYSTEM COMPRISING SEMICONDUCTOR DEVICE A semiconductor device comprises a sense amplifier circuit amplifying a signal transmitted through the bit line, first/second data lines transmitting the signal amplified by the sense amplifier circuit, a read amplifier circuit driven by a first voltage and amplifying t... | 10/27/2011 |
| 20110255351 | Level Shifter with Embedded Logic and Low Minimum Voltage In one embodiment, a level shifter circuit may include a shift stage that also embeds transistors that implement a logic operation on two or more inputs to the level shifter. At least one of the inputs may be sourced from circuitry that is powered by a different power s... | 10/20/2011 |
| 20110249518 | Circuits, Systems, and Methods for Dynamic Voltage Level Shifting Dynamic voltage level shifting circuits, systems and methods are disclosed. A level shifting circuit comprises an input for accepting a first discrete voltage level to be shifted, a level shifting portion coupled to the input and to a second discrete voltage level, an e... | 10/13/2011 |
| 20110242904 | Read Only Memory and Operating Method Thereof A read only memory (ROM) and an operating method thereof are provided. The read only memory includes: a control circuit, powered by a first power source for outputting a control signal within a first voltage range; a voltage shifter, for expanding the amplitude of the c... | 10/06/2011 |
| 20110235442 | Integrated Circuit with Separate Supply Voltage for Memory That is Different from Logic Circuit Supply Voltage In one embodiment, an integrated circuit includes at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written ... | 09/29/2011 |
| 20110228617 | TECHNIQUES FOR REDUCING A VOLTAGE SWING Techniques for reducing a voltage swing are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus for reducing a voltage swing comprising: a plurality of dynamic random access memory cells arranged in arrays of rows and column... | 09/22/2011 |
| 20110211398 | MEMORY DEVICE AND ASSOCIATED MAIN WORD LINE AND WORD LINE DRIVING CIRCUIT A main word line driving circuit for driving word lines in a memory device comprises first and second level shifting units and an inverting unit. The first level shifting unit is configured to convert a decode signal into a first operative signal, and the second level s... | 09/01/2011 |
| 20110205815 | Decoder circuit of semiconductor storage device The present invention provides a row decoder of a semiconductor storage device that prevents an increase in a circuit area while maintaining a high operation speed. Namely, the row decoder of the semiconductor storage device includes a word line selection circuit that h... | 08/25/2011 |
| 20110205814 | SENSE AMPLIFIER AND METHOD OF SENSING DATA USING THE SAME Some embodiments regard a circuit comprising a pre-charge circuit and a latch circuit. The pre-charge circuit charges a voltage node to a pre-determined voltage level based on which the latch circuit generates a feedback signal to stop the pre-charge circuit from chargi... | 08/25/2011 |
| 20110199837 | High Voltage Word Line Driver A word line driver circuit coupled to a memory circuit word line includes pull-up, pull-up clamp, pull-down and pull-down clamp transistors, each having a source, a drain and a gate. For the pull-up transistor, the source is coupled to a first power supply, and the gate... | 08/18/2011 |
| 20110199839 | WEAK BIT COMPENSATION FOR STATIC RANDOM ACCESS MEMORY A static random access memory (SRAM) includes a data line, a data line bar, and a current path block. The current path block includes at least two transistors configured to provide a current path for the data line in transition from a first logic voltage to a second log... | 08/18/2011 |
| 20110194352 | PROGRAMMING METHODS AND MEMORIES Memory devices and programming methods for memories are disclosed, such as those adapted to program a memory using an increasing channel voltage for a first portion of programming, and an increasing but reduced channel voltage for a second portion of programming.... | 08/11/2011 |
| 20110194362 | WORD-LINE DRIVER USING LEVEL SHIFTER AT LOCAL CONTROL CIRCUIT A representative circuit device includes a local control circuit having a level shifter, wherein in response to receipt of a first address signal the level shifter shifts the first address signal from a first voltage level to a second voltage level, providing a level sh... | 08/11/2011 |
| 20110188326 | DUAL RAIL STATIC RANDOM ACCESS MEMORY A static random access memory (SRAM) macro includes a first power supply voltage and a second power supply voltage that is different from the first power supply voltage. A precharge control is connected to the second power supply voltage. The precharge control is couple... | 08/04/2011 |
| 20110158023 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DRIVING THE SAME A semiconductor memory device includes a cell block including a first bit line, a sense amplifier unit including a second bit line and configured to amplify a data signal applied to the second bit line, a connection unit configured to selectively connect the first bit l... | 06/30/2011 |
| 20110158007 | MULTI-POWER DOMAIN DESIGN In some embodiments related to a memory array, a sense amplifier (SA) uses a first power supply, e.g., voltage VDDA, while other circuitry, e.g., signal output logic, uses a second power supply, e.g., voltage VDDB. Various embodiments place the SA and a pair of transfer... | 06/30/2011 |
| 20110149661 | MEMORY ARRAY HAVING EXTENDED WRITE OPERATION In some embodiments, an apparatus comprising a memory array of static random access memory (SRAM) cells arranged in a plurality of rows and a plurality of columns and configured to receive a clock signal having a plurality of clock cycles; a plurality of word-lines asso... | 06/23/2011 |
| 20110141830 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME A semiconductor memory device includes a sense amplifier configured to sense and amplify data loaded into a bit line pair, a power line equalize signal generation unit configured to generate a power line equalize signal which is activated until the bit line sense amplif... | 06/16/2011 |
| 20110134707 | BLOCK ISOLATION CONTROL CIRCUIT A block isolation control circuit includes: a control signal generation unit configured to generate a control signal which is disabled when a defect occurs in a cell block and it is necessary to replace a defective cell block with a redundant cell block, or when the cel... | 06/09/2011 |
| 20110134710 | Level shift circuit A feedback circuit by which an output of a memory device for storing level-shifted data can be fed back to the input side includes inverters, resistors, and transistors. The resistance value of combined resistance for pulling up or down first and second switching device... | 06/09/2011 |
| 20110128799 | LEVEL SHIFTING CIRCUIT AND NONVOLATILE SEMICONDUCTOR MEMORY APPARATUS USING THE SAME A nonvolatile semiconductor memory apparatus includes a control unit configured to generate a select signal and a driving control signal in response to a first enable signal and a second enable signal; a level shifting unit configured to enable a first shifting signal o... | 06/02/2011 |
| 20110122712 | Controlling voltage levels applied to access devices when accessing storage cells in a memory A semiconductor memory storage device is disclosed. This memory device has a plurality of storage cells for storing data; a plurality of access devices for allowing access to the corresponding plurality of storage cells, the plurality of access devices being arranged in... | 05/26/2011 |
| 20110085389 | METHOD AND SYSTEM TO LOWER THE MINIMUM OPERATING VOLTAGE OF A MEMORY ARRAY A method and system to lower the minimum operating voltage of a memory array during read and/or write operations of the memory array. In one embodiment of the invention, the voltage of the read and/or write word line of the memory array is boosted or increased during re... | 04/14/2011 |
| 20110085390 | WORD-LINE LEVEL SHIFT CIRCUIT A dual word-line level shifter circuit and associated SRAM. A circuit is disclosed that includes a first transistor gated by a data input at the lower voltage, and a second transistor gated by a restore input at the higher voltage, wherein the first and second transisto... | 04/14/2011 |
| 20110080793 | SENSING AMPLIFIER APPLIED TO AT LEAST A MEMORY CELL, MEMORY DEVICE, AND ENHANCEMENT METHOD FOR BOOSTING THE SENSING AMPLIFIER THEREOF A sensing amplifier consists of a sensing circuit, a boosting circuit, at least one bit-line isolating circuit, and at least a P-sensing enhancement circuit. The sensing circuit is disposed between a sensing line and a complementary sensing line. The boosting circuit bo... | 04/07/2011 |
| 20110075491 | SEMICONDUCTOR MEMORY APPARATUS AND METHOD OF DRIVING BIT-LINE SENSE AMPLIFIER Disclosed is a semiconductor memory apparatus which improves the time to transmit write data to a memory cell and improves data retention time of the memory cell. To this end, the semiconductor memory apparatus includes a bit-line sense amplifier that senses and amplifi... | 03/31/2011 |
