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| Application No. | Application Title | Issue Date |
| 20120106263 | INPUT/OUTPUT CIRCUIT AND METHOD OF SEMICONDUCTOR APPARATUS AND SYSTEM WITH THE SAME A system includes a controller which is capable of operating at one of a first speed and a second speed slower than the first speed; a semiconductor memory apparatus operating at the first speed; and an input/output device which is connected between the semiconductor me... | 05/03/2012 |
| 20120106264 | WRITE-LEVELING IMPLEMENTATION IN PROGRAMMABLE LOGIC DEVICES Circuits, methods, and apparatus for memory interfaces that compensate for skew between a clock signal and DQ/DQS signals that may be caused by a fly-by routing topology. The skew is compensated by clocking the DQ/DQS signals with a phase delayed clock signal, where the... | 05/03/2012 |
| 20120072790 | On-Chip Memory Testing An integrated circuit is described that has a substrate with a memory array with dedicated support hardware formed on the substrate. An access wrapper circuit is coupled to address and data lines of the memory array and to control lines of the dedicated support hardware... | 03/22/2012 |
| 20120051148 | VOLTAGE SIGNALS MULTIPLEXER A voltage signal multiplexer includes a control and bias stage to generate at least one control and bias signal as a function of first and second selection signals and first and second input voltage signals. The multiplexer further comprises a switching stage configured... | 03/01/2012 |
| 20120051149 | SEMICONDUCTOR APPARATUS AND DATA WRITE CIRCUIT OF SEMICONDUCTOR APPARATUS A data write circuit of a semiconductor apparatus includes a plurality of latches configured to latch a plurality of data in response to activation of a plurality of control signals and output the latched data to data lines; and a control unit configured to generate the... | 03/01/2012 |
| 20120008420 | Command Generation Circuit And Semiconductor Memory Device There is provided a command generation circuit. The command generation circuit includes a first driving unit driving an output node in response to an internal MRS command and a RAS idle signal; a second driving unit driving the output node in response to an off-signal; ... | 01/12/2012 |
| 20110317494 | PIPE LATCH CIRCUIT OF MULTI-BIT PREFETCH-TYPE SEMICONDUCTOR MEMORY DEVICE WITH IMPROVED STRUCTURE Provided is a pipe latch circuit of a multi-bit pre-fetch type semiconductor memory device with an advanced structure. The pipe latch circuit of the present invention comprises: a first latch circuit for latching pre-fetched plural bits of input data from global input/o... | 12/29/2011 |
| 20110249510 | EMBEDDED STORAGE APPARATUS AND TEST METHOD THEREOF An embedded storage apparatus including a control unit, a storage unit, and a signal processing and measurement unit is provided. The control unit outputs a plurality of signals, wherein the signals include a mode selection signal and a plurality of control signals. The... | 10/13/2011 |
| 20110249511 | SEMICONDUCTOR DEVICE A semiconductor device includes a termination driver for driving a data line with a predetermined termination level by using an external power supply voltage and a drive current controller for controlling a drive current flowing into the data line from the termination d... | 10/13/2011 |
| 20110242905 | SEMICONDUCTOR MODULE INCLUDING MODULE CONTROL CIRCUIT AND METHOD FOR CONTROLLING THE SAME A module control circuit includes an input unit configured to receive a plurality of data signals from a plurality of data input/output pins and output an identification signal and an internal command signal. A latch unit is configured to latch the identification signal... | 10/06/2011 |
| 20110216605 | TECHNIQUES FOR PROVIDING A SEMICONDUCTOR MEMORY DEVICE HAVING HIERARCHICAL BIT LINES Techniques for providing a semiconductor memory device having hierarchical bit lines are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells and a plurality of local bit... | 09/08/2011 |
| 20110211384 | STATIC RANDOM-ACCESS MEMORY WITH BOOSTED VOLTAGES Dual port memory elements and memory array circuitry that utilizes elevated and non-elevated power supply voltages for performing reliable reading and writing operations are provided. The memory array circuitry may contain circuitry to switch a power supply line of a co... | 09/01/2011 |
| 20110211397 | PIPE LATCH CIRCUIT AND METHOD FOR OPERATING THE SAME A pipe latch circuit includes a division unit configured to output a division signal, a multiplexing unit configured to multiplex a plurality of source signals according to periods determined by the division signal and generate a plurality of pipe input control signals,... | 09/01/2011 |
| 20110199835 | No-Disturb Bit Line Write for Improving Speed of eDRAM A method of operating a memory circuit includes providing the memory circuit. The memory circuit includes a memory cell; a word line connected to the memory cell; a first local bit line and a second local bit line connected to the memory cell; and a first global bit lin... | 08/18/2011 |
| 20110194358 | SEMICONDUCTOR MEMORY DEVICE USING INTERNAL HIGH POWER SUPPLY VOLTAGE IN SELF-REFRESH OPERATION MODE AND RELATED METHOD OF OPERATION A semiconductor memory device comprises a memory cell array comprising a plurality of memory banks. The semiconductor memory device performs refresh operations on the memory cell array using a normal refresh operation mode and a self-refresh operation mode. In the norma... | 08/11/2011 |
| 20110194328 | VARIABLE RESISTANCE MEMORY DEVICE AND RELATED METHOD OF OPERATION A variable resistance memory device comprises a variable resistance memory cell, a switch that selectively passes a write voltage to an input terminal of the variable resistance memory cell, and a trigger circuit that controls the switch to cut off the write voltage fro... | 08/11/2011 |
| 20110164459 | LIST STRUCTURE CONTROL CIRCUIT A list structure control circuit includes memories each individually stores data, selection circuits arranged for each of the memories and series-connect the memories so that data stored in each memory has an order relation, and an update control circuit that adds a pos... | 07/07/2011 |
| 20110149984 | CONFIGURATION MEMORY APPARATUS IN FPGA AND ROUTER SYSTEM USING THE SAME Disclosed are a configuration memory apparatus and a router system using the same. The configuration memory apparatus includes: a selection unit selecting one of a first external device and a storage unit and receiving data; a register storing input data received from t... | 06/23/2011 |
| 20110134705 | INTEGRATED CIRCUIT PACKAGE WITH MULTIPLE DIES AND A MULTIPLEXED COMMUNICATIONS INTERFACE A package includes a first die and a second die, at least one of said first and second dies being a memory. The dies are connected to each other through an interface. The interface is configured to transport both control signals and memory transactions. A multiplexer is... | 06/09/2011 |
| 20110128793 | PREAMBLE DETECTION AND POSTAMBLE CLOSURE FOR A MEMORY INTERFACE CONTROLLER A memory controller, such as a memory controller for reading data received from a DDR SDRAM memory, may detect the beginning and end of a read cycle. The memory controller may include a preamble detection circuit to receive a strobe signal and output a first control sig... | 06/02/2011 |
| 20110128781 | SEMICONDUCTOR MEMORY CIRCUIT A semiconductor memory circuit includes a memory cell array having a plurality of memory cells arranged in a row direction and a column direction; a row selecting unit for selecting the memory cells of the memory cell array aligned in the row direction; a column selecti... | 06/02/2011 |
| 20110110164 | TRIM CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE COMPRISING SAME A trim circuit comprises a trim code storage unit, a global latch unit and a local latch unit. The trim code storage unit stores a plurality of trim codes and outputs a sensing code in response to an address signal. The global latch unit latches a calibrated code or the... | 05/12/2011 |
| 20110085387 | SEMICONDUCTOR MEMORY APPARATUS WITH CLOCK AND DATA STROBE PHASE DETECTION A semiconductor memory apparatus includes an internal tuning unit configured to tune a generation timing of a data input strobe signal according to a phase difference between an external clock signal and a data strobe clock signal, and a data input sense amplifier confi... | 04/14/2011 |
| 20110063906 | MEMORY ADAPTED TO PROGRAM A NUMBER OF BITS TO A MEMORY CELL AND READ A DIFFERENT NUMBER OF BITS FROM THE MEMORY CELL A memory has a memory array with a memory cell. The memory is adapted to program a first number of bits into the memory cell. The memory is adapted to sense a second number of bits, different from the first number of bits, from the memory cell.... | 03/17/2011 |
| 20100315886 | DATA TRANSFER APPARATUS, AND METHOD, AND SEMICONDUCTOR CIRCUIT Provided is a data transfer apparatus and method that enables fast data transfer, and has a simple circuit configuration and a small area; and a semiconductor circuit. The data transfer apparatus includes: a data pair generation circuit (301) that transfers a gen... | 12/16/2010 |
| 20100315885 | CIRCUITS, DEVICES, SYSTEMS, AND METHODS OF OPERATION FOR CAPTURING DATA SIGNALS Embodiments of the invention are described for driving data onto a data bus. The embodiments include a data driver circuit having a data capture circuit coupled to the data bus. The data capture circuit receives a data signal relative to a write strobe signal and captur... | 12/16/2010 |
| 20100309732 | DATA ALIGNMENT CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS A data alignment circuit of a semiconductor memory apparatus for receiving and aligning parallel data group includes a first control unit, a second control unit, a first alignment unit and a second alignment unit. The first alignment unit generates a first control signa... | 12/09/2010 |
| 20100309731 | KEEPERLESS FULLY COMPLEMENTARY STATIC SELECTION CIRCUIT Selection circuitry for use in register files, multiplexers, and so forth is disclosed. The selection circuitry includes a plurality of local bit lines coupled to global bit line circuitry. Groups of cells or data inputs are coupled to each of the local bit lines. When ... | 12/09/2010 |
| 20100284214 | ELECTRONICALLY SCANNABLE MULTIPLEXING DEVICE An electronically scannable multiplexing device is capable of addressing multiple bits within a volatile or non-volatile memory cell. The multiplexing device generates an electronically scannable conducting channel with two oppositely formed depletion regions. The deple... | 11/11/2010 |
| 20100272265 | SYSTEM AND METHOD TO CONTROL ONE TIME PROGRAMMABLE MEMORY Systems and methods to control one time programmable (OTP) memory are disclosed. A method may include determining a functionality for a hardware capability bus in an integrated circuit. The method may also include storing data in a first register of the integrated circu... | 10/28/2010 |
| 20100246275 | METHODS AND APPARATUS RELATED TO A SHARED MEMORY BUFFER FOR VARIABLE-SIZED CELLS In one embodiment, an apparatus includes a shared memory buffer including a lead memory bank and a write multiplexing module configured to send a leading segment from a set of segments to the lead memory bank. The set of segments includes bit values from a set of variab... | 09/30/2010 |
| 20100246276 | Semiconductor memory device having swap function for data output pads A semiconductor memory device having a status register read function includes a plurality of data output pads electrically connected to corresponding package pin, and a swap controller connected between the plurality of data output pads and a plurality of output lines t... | 09/30/2010 |
| 20100220534 | Memory Device with Reduced Buffer Current During Power-Down Mode A memory device comprises a memory array, at least one buffer coupled to the memory array, and test circuitry coupled to the buffer. The buffer comprises switching circuitry configured to multiplex first and second inputs of the buffer to a given output of the buffer ba... | 09/02/2010 |
| 20100208538 | SENSING CIRCUIT FOR SEMICONDUCTOR MEMORY A sensing circuit for a semiconductor memory includes a multiplexer coupled to a bit line and a data line coupling the multiplexer to a sense amplifier. The data line is configured to be precharged to a voltage level higher than a precharge voltage level of the bit line... | 08/19/2010 |
| 20100202218 | System and Method for Level Shifter In one embodiment, a bit-line interface is disclosed. The bit-line interface has a multiplexer having a plurality of bit-line outputs, and a write path coupled to a multiplexer signal input. The bit-line interface also has a read path coupled to the multiplexer signal i... | 08/12/2010 |
| 20100165749 | Sense Amplifier Used in the Write Operations of SRAM A static random access memory (SRAM) circuit includes a pair of complementary global bit-lines, and a pair of complementary local bit-lines. A global read/write circuit is coupled to, and configured to write a small-swing signal to, the pair of global bit-lines in a wri... | 07/01/2010 |
| 20100128509 | Three-Dimensional Semiconductor Devices and Methods of Operating the Same Provided are a three-dimensional semiconductor device and a method of operating the same. The three-dimensional semiconductor device includes: a plurality of word line structures on a substrate; active semiconductor patterns between the plurality of word line structures... | 05/27/2010 |
| 20100118615 | Semiconductor memory device A semiconductor memory device includes a sub memory cell array region having memory cells each connected between word lines extending in a first direction and bit lines extending in a second direction that is orthogonal to the first direction of extension of the word li... | 05/13/2010 |
| 20100118616 | Semiconductor memory device A semiconductor memory device having shared sense amplifiers is provided. The semiconductor memory device has a bit-line selector disposed closer to a memory cell array than a column decoder. When the column decoder outputs a bit-line indication signal corresponding to ... | 05/13/2010 |
| 20100118614 | SEMICONDUCTOR APPARATUS, DATA WRITE CIRCUIT OF SEMICONDUCTOR APPARATUS, AND METHOD OF CONTROLLING DATA WRITE CIRCUIT A data write circuit of a semiconductor apparatus includes a plurality of latches configured to latch a plurality of data in response to activation of a plurality of control signals and output the latched data to data lines; and a control unit configured to generate the... | 05/13/2010 |
