Did You Know...
...that a workman who left the soap mixing machine on too long was responsible for making Ivory Soap? He was so embarrassed by his mistake that he threw the mess in a stream. Imagine his dismay when the evidence of his error floated to the surface! Result: Ivory soap, the soap that floats.
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| Application No. | Application Title | Issue Date |
| 20070286002 | METHOD FOR WRITING TO MULTIPLE BANKS OF A MEMORY DEVICE In a multi-bank memory system such as a synchronous dynamic random access memory (SDRAM), a method of writing data to the banks is provided. This method allows for writing to any number of banks. More particularly, this method allows for writing to a selected number of ... | 12/13/2007 |
| 20070280006 | Data processing device, data processing method, and program A data processing device for processing time-sequence data includes a data extracting unit operable to extract time-sequence data for a predetermined time unit from time-sequence data; and a processing unit operable to obtain scores for nodes of an SOM configured from m... | 12/06/2007 |
| 20070268756 | Memory device and method having low-power, high write latency mode and high-power, low write latency mode and/or independently selectable write latency A logic circuit operates write receivers in a dynamic random access memory device in either a low-power mode, high write latency mode or a high-power mode, low write latency mode. The logic circuit receives a first signal indicative of whether the high-power, low write ... | 11/22/2007 |
| 20070268755 | Memory circuit A memory circuit is provided comprising a memory cell, a pair of conducting lines operable to signal the logic state of the memory cell and read circuitry operable to perform a read operation by detecting a voltage level of at least one of the pair of conducting lines. ... | 11/22/2007 |
| 20070263425 | MEMORY ARRANGEMENT A memory arrangement is disclosed. In one embodiment, the control device includes a plurality of memory arrays for storing data and a control device for controlling the transfer of data between the plurality of memory arrays and external circuits. In one embodiment, the... | 11/15/2007 |
| 20070242532 | Integrated Circuit Memory Device Having Delayed Write Timing Based on Read Response Time An integrated circuit memory device includes a first set of pins and a memory core. The first set of pins receive, using a clock signal, a write command and a read command. Control information is issued internally in response to the write command after a predetermined d... | 10/18/2007 |
| 20070242528 | Nonvolatile semiconductor memory device A nonvolatile semiconductor memory device comprises a memory cell array in which memory cells are arranged in a row and column direction, a circuit for applying a first voltage to a selected bit line, a circuit for applying a second voltage to unselected bit lines and w... | 10/18/2007 |
| 20070242529 | Method and Apparatus for Accessing Contents of Memory Cells The invention relates to accessing contents of memory cells. Some embodiments include a memory structure that has a first cell, a second cell, and a sense amplifier. The first cell stores a first value. The first and second cells are connected to the sense amplifier by ... | 10/18/2007 |
| 20070242526 | SEMICONDUCTOR MEMORY AND READ METHOD OF THE SAME According to the present invention, there is provided a semiconductor memory comprising a memory cell which is a MOSFET formed on an SOI substrate and having a gate electrode connected to a word line, a drain region connected to a bit line, and a grounded source region,... | 10/18/2007 |
| 20070242527 | SEMICONDUCTOR MEMORY DEVICE FOR STORING MULTILEVEL DATA In a memory cell array, a plurality of memory cells are arranged in a matrix. Each of the plurality of memory cells stores one of a plurality of threshold levels. When writing one of the plurality of threshold levels into a first memory cell of the memory cell array, a ... | 10/18/2007 |
| 20070237006 | Method for generating soft bits in flash memories Information stored as physical states of cells of a memory is read by setting each of one or more references to a respective member of a first set of values and reading the physical states of the cells according to the first set. Then, at least some of the references ar... | 10/11/2007 |
| 20070211542 | Multi-probe for writing and reading data and method of operating the same A multi-probe for writing data to and/or reading data from a recording medium. The multi-probe includes a plurality of probes. All of the probes are working probes for writing the data to and/or reading the data from the recording medium. ... | 09/13/2007 |
| 20070211543 | Semiconductor device with non-volatile memory and random access memory A semiconductor device including a large capacity non-volatile memory and at least one random access memory, said the access time of said device being matched to the access time of each random access memory. The semiconductor memory device is comprised of: a non-volatil... | 09/13/2007 |
| 20070195612 | METHODS AND SYSTEMS FOR CREATING DATA SAMPLES FOR DATA ANALYSIS Systems and methods for creating data samples for data analysis. The method includes imaging at least a portion of a first object having a target portion to generate a first image, analyzing the first image by running a first series of algorithms using the first image t... | 08/23/2007 |
| 20070195611 | Programmable structure, a memory, a display and a method for reading data from a memory cell The invention refers to an improved programmable structure, an improved memory, an improved display and an improved method for reading data from a memory cell. More particularly, embodiments of the invention provide a programmable structure and a memory, whereby a progr... | 08/23/2007 |
| 20070189089 | Method and Apparatus for Implementing High Speed Memory Various methods and apparatuses permit high speed reads of memory. Portions of data are copied and stored on other word lines. By reading a copy of data that is stored on memory cells accessed by a word line that is already precharged, a latency specification can be met... | 08/16/2007 |
| 20070171732 | ORGANIC MEMORY An organic memory is provided. The organic memory at least comprises a plurality of select lines, a plurality of data lines, a bit cell array, and a plurality of digital sensing circuits. The bit cell array comprises a plurality of bit cells, wherein each bit cell compr... | 07/26/2007 |
| 20070171733 | TIMING CIRCUIT CAD A method of generating a design for timing circuitry having plural rotary travelling wave component circuit sections, comprise steps of first dividing an area to be serviced into regions each small enough for there to be negligible inter-region transmission-line delay a... | 07/26/2007 |
| 20070171731 | Leakage mitigation logic Leakage current from a circuit for handling data is reduced using leakage control circuit operable in a leakage reduction mode. The data handling circuit comprises data handling logic operable to receive an input data value and to output and output data value. The data ... | 07/26/2007 |
| 20070159871 | Semiconductor device with a non-erasable memory and/or a nonvolatile memory A semiconductor device comprises a plurality of memory cells, a central processing unit, a timer circuit which times a RESET time, and a timer circuit which times a SET time. A threshold voltage of an NMOS transistor of each memory cell is lower than that of the periphe... | 07/12/2007 |
| 20070162685 | Memory data bus structure and method of transferring information with plural memory banks A data bus structure for a dynamic random access memory (DRAM) according to the present invention includes a series of data buses, each shared by a plurality of memory banks, and a switching device to selectively couple the data buses to a global data bus to enable the ... | 07/12/2007 |
| 20070159894 | Memory cell, read device for memory cell, memory assembly, and corresponding method A memory cell includes transistors and two read ports. Each read port is configured to be connected to a read line. The memory cell is configured such that in a read operation of the memory cell an information stored in the memory cell is readable by a differential read... | 07/12/2007 |
| 20070133309 | Memory with a memory cell comprising a MOS transistor with an isolated body and method of accessing A dynamic random access memory (DRAM) comprising memory cells distributed in rows and in columns, each memory cell comprising a MOS transistor with a floating body, the memory comprising circuitry for writing a datum into a determined (i.e. selected) memory cell belongi... | 06/14/2007 |
| 20070109873 | Non-volatile memory device having controlled bulk voltage and method of programming same Disclosed is a non-volatile memory device and a method of programming the same. The non-volatile memory device is programmed by applying a wordline voltage, a bitline voltage, and a bulk voltage to memory cells within the device. During a programming operation for the d... | 05/17/2007 |
| 20070097751 | Method and apparatus for varying the programming duration and/or voltage of an electrically floating body transistor, and memory cell array implementing same There are many inventions described herein as well as many aspects and embodiments of those inventions, for example, circuitry and techniques for reading, writing and/or operating a semiconductor memory cells of a memory cell array, including electrically floating body ... | 05/03/2007 |
| 20070091688 | Method of programming a non-volatile memory cell The present invention relates to a method of programming a select non-volatile memory cell in a plurality of serially connected non-volatile memory cells with a serially connected select transistor. Each of the non-volatile memory cells has a control gate for receiving ... | 04/26/2007 |
| 20070081395 | Semiconductor memory device having low power consumption type column decoder and read operation method thereof The present invention relates to a semiconductor memory device having a low power consumption type column decoder and read operation method thereof. In accordance with the semiconductor memory device and read operation method thereof according to the present invention, ... | 04/12/2007 |
| 20070076491 | Multibit memory cell Provided are a method, system and device for storing multiple bits into a multibit memory cell. In the illustrated embodiment, each multibit memory cell is a “quadbit” cell capable of storing 4 bits which are read out on four bit lines of the cell in response to act... | 04/05/2007 |
| 20070070710 | Nonvolatile semiconductor memory device and data writing method The present invention aims to eliminate variations in threshold voltage subsequent to the writing of data in an EPROM. When a parasitic resistance between the source of a memory cell (M00) of an even-numbered row and its corresponding bit line (BL0) is lar... | 03/29/2007 |
| 20070070709 | Write circuit of memory device A write circuit of a semiconductor memory device includes a global data input/output (I/O) line; an amplifying block for receiving and amplifying write data and transmitting the amplified write data as global data onto the global data I/O line; and a control block for c... | 03/29/2007 |
| 20070070711 | Driving signal generator for bit line sense amplifier driver A semiconductor memory device includes an over driver for driving a pull-up power line of a bit line sense amplifier by an over driving signal, a normal driver for driving the pull-up power line of the bit line sense amplifier by a normal driving signal, and a driving s... | 03/29/2007 |
| 20070058447 | Technique to suppress bitline leakage current Methods and apparatus that may help reduce standby current in memory devices are provided. By separating equalizing and precharging functions into separate circuit structures, current paths between a source of precharge voltage and a defective wordline (e.g., having an ... | 03/15/2007 |
| 20070058449 | Semiconductor device and method thereof A semiconductor device and method thereof. The semiconductor device may include a protection unit receiving an input signal and outputting a switching control signal based on the received input signal, the received input signal indicating an operating mode of a controll... | 03/15/2007 |
| 20070058448 | Bitline variable methods and circuits for evaluating static memory cell dynamic stability Bitline variable methods and circuits for evaluating static memory cell dynamic stability provide a mechanism for raising the performance of memory arrays beyond present levels/yields. By altering the bitline pre-charge voltage of a static random access memory (SRAM) me... | 03/15/2007 |
| 20070041250 | READ PORT CIRCUIT FOR REGISTER FILE In one embodiment, a read port circuit comprises a precharge circuit configured to precharge a first node in the read port circuit and a pulldown circuit coupled to the first node. The pulldown circuit is configured to conditionally discharge the first node responsive t... | 02/22/2007 |
| 20070036004 | Hybrid non-volatile memory device The present invention discloses a memory device that includes a first memory cell array for storing one or more codes; a second memory cell array for storing one or more data, which are updated substantially more frequently than the codes; and a third memory cell array ... | 02/15/2007 |
| 20070030738 | Technique to suppress leakage current Embodiments of the invention generally provide a method and wordline driver having a reduced leakage current. In one embodiment, a wordline is driven to a boosted high voltage with a driver transistor of the wordline driver if the wordline driver is in an operational mo... | 02/08/2007 |
| 20070028029 | METHOD AND APPARATUS FOR DATA TRANSFER A method and apparatus for data transfer includes receiving a first data packet across a first bi-directional bus and receiving a second data packet across a second bi-directional bus. Next, the first data packet is written to a first register operably coupled to the fi... | 02/01/2007 |
| 20070008785 | Apparatus and method for programming an array of nonvolatile memory cells including switchable resistor memory elements A non-volatile memory cell includes a switchable resistor memory element in series with a switch device. An array of such cells may be programmed using only positive voltages. A method for programming such cells also supports a direct write of both 0 and 1 data states w... | 01/11/2007 |
| 20070008784 | Two-bit per I/O line write data bus for DDR1 and DDR2 operating modes in a DRAM A data bus circuit for an integrated circuit memory includes a 4-bit bus per I/O pad that is used to connect the memory with an I/O block, but only two bits per I/O are utilized for writing. Four bits per I/O pad are used for reading. At every falling edge of an input d... | 01/11/2007 |
