Celebrity Inventors
Glam girl Heddy Lamar may have used her good looks to good effect on the silver screen, but she put her smarts to better use as an inventor. During World War II, she co-patented a frequency-switching system for torpedo guidance that was considered years ahead of its time.
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| Application No. | Application Title | Issue Date |
| 20120069678 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR DRIVING THE SAME A storage device according to one embodiment includes memory cells which are connected in series in a first direction and are arranged in a matrix by the arranged series connections, and word lines which connect control gates of the memory cells in a second direction pe... | 03/22/2012 |
| 20120069680 | NAND WITH BACK BIASED OPERATION Methods of programming, reading and erasing memory cells are disclosed. In at least one embodiment, program, sense, and erase operations in a memory are performed with back biased operation, such as to improve high voltage device isolation and cutoff in string drivers a... | 03/22/2012 |
| 20120069679 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DRIVING SAME According to one embodiment, a nonvolatile semiconductor memory device includes a memory string including a plurality of memory cells and, a driving unit. In sequentially reading data stored in the memory cells by applying a first signal to the memory cells, a second si... | 03/22/2012 |
| 20120051130 | SYSTEM AND METHOD FOR DETECTING DISTURBED MEMORY CELLS OF A SEMICONDUCTOR MEMORY DEVICE A method of detecting a disturb condition of a memory cell includes application of multiple sets of conditions to the memory cell and determining whether the memory cell behaves as a programmed memory cell in response to the sets of conditions. A disturbed memory cell c... | 03/01/2012 |
| 20120051139 | REDUCING READ FAILURE IN A MEMORY DEVICE Read failure is reduced by increasing the drain current through a serial string of memory cells during the read operation. In one embodiment, this is accomplished by using a higher read pass voltage for unselected word lines when the selected word line is within a prede... | 03/01/2012 |
| 20120044772 | NON-VOLATILE MEMORY DEVICE, SYSTEM, AND CELL ARRAY A non-volatile memory cell array, comprising sector selection transistors controlled by a voltage applied to sector selection lines, first through fourth memory cells connected in series to the sector selection transistors, a first common source line connected between t... | 02/23/2012 |
| 20120044765 | WORD LINE ACTIVATION IN MEMORY DEVICES Memory devices and methods are disclosed, such as those facilitating flexibility in applying differing biasing schemes to word lines. For example, one such memory device can include an architecture capable of partitioning word lines into one of a plurality of address sp... | 02/23/2012 |
| 20120033491 | PROGRAMMING OF MEMORY CELLS IN A NONVOLATILE MEMORY USING AN ACTIVE TRANSITION CONTROL An electrically programmable non-volatile memory array and associated circuitry, including programming circuitry that adaptively senses completed programming of a selected memory cell. A programming bit line driver is connected to the bit line, and a first transistor ha... | 02/09/2012 |
| 20120026800 | SEMICONDUCTOR APPARATUS AND METHOD FOR TRANSFERRING CONTROL VOLTAGE A semiconductor apparatus includes a control voltage transfer unit configured to transfer a control voltage transmitted through first transmission lines, to second transmission lines in response to a select signal transmitted through a select signal transmission line; a... | 02/02/2012 |
| 20120014181 | Nonvolatile Semiconductor Memory A hot electron (BBHE) is generated close to a drain by tunneling between bands, and it data writing is performed by injecting the hot electron into a charge storage layer. When Vg is a gate voltage, Vsub is a cell well voltage, Vs is a source voltage and Vd is a drain v... | 01/19/2012 |
| 20120014185 | CIRCUITS, SYSTEMS AND METHODS FOR DRIVING HIGH AND LOW VOLTAGES ON BIT LINES IN NON-VOLATILE MEMORY An integrated circuit bit line driver system includes a plurality of bit line drivers coupled to respective bit lines of an array of non-volatile memory cells. Each of the bit line drivers includes a bias transistor through which an input signal is coupled to the respec... | 01/19/2012 |
| 20110310673 | MULTI-PAGE PROGRAM METHOD, NON-VOLATILE MEMORY DEVICE USING THE SAME, AND DATA STORAGE SYSTEM INCLUDING THE SAME A method of programming a non-volatile memory device including a plurality of strings arranged in rows and columns comprises activating all or a part of selection lines in one column at the same time depending upon data to be programmed, driving a bit line corresponding... | 12/22/2011 |
| 20110310674 | System and Method for Bit-Line Control In one embodiment, a bit-line driver is disclosed. The driver has a first driver having a source terminal coupled to a high-voltage supply bus and a drain terminal coupled to the bit-line, and a second driver having a source terminal coupled to a high-voltage return bus... | 12/22/2011 |
| 20110310668 | Flash Memory Device and Program Method Thereof A nonvolatile memory device that includes first and second storage areas, and a control logic configured to control the first and second storage areas, wherein when a program operation of the first storage area is passed before a program operation of the second storage ... | 12/22/2011 |
| 20110267891 | DRIVING CIRCUIT FOR MEMORY DEVICE An electrically programmable non-volatile memory device is proposed. The memory device includes a plurality of memory cells and a driver circuit for driving the memory cells; the driver circuit includes programming means for providing a first programming voltage and a s... | 11/03/2011 |
| 20110255346 | SUB VOLT FLASH MEMORY SYSTEM Various circuits include MOS transistors that have a bulk voltage terminal for receiving a bulk voltage that is different from a supply voltage and ground. The bulk voltage may be selectively set so that some MOS transistors have a bulk voltage set to the supply voltage... | 10/20/2011 |
| 20110242904 | Read Only Memory and Operating Method Thereof A read only memory (ROM) and an operating method thereof are provided. The read only memory includes: a control circuit, powered by a first power source for outputting a control signal within a first voltage range; a voltage shifter, for expanding the amplitude of the c... | 10/06/2011 |
| 20110228608 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE According to one embodiment, a nonvolatile semiconductor memory device comprises a first memory cell, a second memory cell, and a control circuit. The first memory cell is connected to a first word line. The second memory cell is connected to a second word line which is... | 09/22/2011 |
| 20110228611 | System and Method for Bit-Line Control In one embodiment, a bit-line driver has a first driver having a source terminal coupled to a high-voltage supply bus and a drain terminal coupled to the bit-line, and a second driver having a source terminal coupled to a high-voltage return bus and a drain terminal cou... | 09/22/2011 |
| 20110222339 | NONVOLATILE MEMORY DEVICE FOR REDUCING INTERFERENCE BETWEEN WORD LINES AND OPERATION METHOD THEREOF Provided are a nonvolatile memory device and a method of operating the same. The nonvolatile memory device in accordance with an embodiment of the inventive concept may include a string select line; a ground select line; a dummy word line adjacent to the ground select l... | 09/15/2011 |
| 20110216603 | Non-Volatile Memory Device, Erasing Method Thereof, And Memory System Including The Same Provided is an erasing method of a nonvolatile memory device. The erasing method applies a word line erase voltage to a plurality of word lines connected to the memory cells respectively, applies a specific voltage to a ground selection line connected to the ground sele... | 09/08/2011 |
| 20110205808 | SEMICONDUCTOR MEMORY AND SYSTEM A semiconductor memory includes a plurality of nonvolatile memory cells arranged in a matrix and coupled to control gate lines, selection gate lines, bit lines, and source lines, and includes a source line control unit. The source line control unit, at a time of program... | 08/25/2011 |
| 20110199833 | NON-VOLATILE MEMORY DEVICES, OPERATING METHODS THEREOF AND MEMORY SYSTEMS INCLUDING THE SAME Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be c... | 08/18/2011 |
| 20110199828 | NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING SAME A nonvolatile memory device comprises a bulk region and a plurality of memory cells connected to a source line and a plurality of wordlines. The method comprises applying a source line voltage to the source line with a first magnitude, applying a bulk voltage to the bul... | 08/18/2011 |
| 20110176370 | NONVOLATILE SEMICONDUCTOR MEMORY A nonvolatile semiconductor memory comprises a memory cell array in which a plurality of memory cell transistors capable of storing data according to a threshold voltage; a row decoder having a plurality of transfer MOS transistors connected at first ends to a plurality... | 07/21/2011 |
| 20110157996 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell transistor, a word line, a row decoder, a sense amplifier which determines the data in the memory cell transistor via the bit line, a first bit line clamp transistor connected ... | 06/30/2011 |
| 20110141821 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME A non-volatile semiconductor storage device includes: a substrate; a control circuit layer provided on the substrate; a support layer provided on the control circuit layer; and a memory cell array layer provided on the support layer. The memory cell array layer includes... | 06/16/2011 |
| 20110141820 | SEMICONDUCTOR MEMORY DEVICE INCLUDING STACKED GATE HAVING CHARGE ACCUMULATION LAYER AND CONTROL GATE AND METHOD OF WRITING DATA TO SEMICONDUCTOR MEMORY DEVICE A semiconductor memory device includes memory cells, word lines, a driver circuit, and a control circuit. The driver circuit repeats a programming operation of selecting any one of the word lines, of applying a first voltage to selected one of the word lines, and of app... | 06/16/2011 |
| 20110128787 | RIPPLE PROGRAMMING OF MEMORY CELLS IN A NONVOLATILE MEMORY An electrically erasable programmable read-only memory (EEPROM) with a ripple programming mode. Memory cells in an the EEPROM array include floating-gate transistors with control gates coupled to corresponding word lines, and drain electrodes coupled to corresponding bi... | 06/02/2011 |
| 20110128786 | MEMORY DEVICE A memory device includes a memory sector including a memory sector, a row of select transistors and a number of drivers. The memory sector includes a plurality of word lines each couples to a plurality of memory cells. The row of select transistors select the memory sec... | 06/02/2011 |
| 20110128792 | SEMICONDUCTOR STORAGE DEVICE AND BOOSTING CIRCUIT A boosting circuit includes first to fourth rectification elements, first to fourth MOS transistors, first to fourth capacitors, and a switch circuit. The switch circuit has a low level terminal connected to a first connection node between the first end of the third rec... | 06/02/2011 |
| 20110122693 | FLASH MEMORY ARRAY SYSTEM INCLUDING A TOP GATE MEMORY CELL A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. Th... | 05/26/2011 |
| 20110116321 | SEMICONDUCTOR DEVICE FOR PREVENTING ERRONEOUS WRITE TO MEMORY CELL IN SWITCHING OPERATIONAL MODE BETWEEN NORMAL MODE AND STANDBY MODE When an operational mode is shifted to a standby mode, a first transistor is brought into a conduction state by a control signal, and a word line is thereby clamped to a ground voltage. Further, a second transistor is brought into a non-conduction state, and supply of a... | 05/19/2011 |
| 20110110159 | Nonvolatile Memory Device for Preventing Program Disturbance and Method of Programming the Nonvolatile Memory Device A nonvolatile memory device for preventing program disturbances includes a memory cell array block, a word line driver, and a well bias control unit. The memory cell array block includes at least one cell string having a plurality of memory cells serially connected to a... | 05/12/2011 |
| 20110110164 | TRIM CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE COMPRISING SAME A trim circuit comprises a trim code storage unit, a global latch unit and a local latch unit. The trim code storage unit stores a plurality of trim codes and outputs a sensing code in response to an address signal. The global latch unit latches a calibrated code or the... | 05/12/2011 |
| 20110110163 | WORD LINE DRIVERS IN NON-VOLATILE MEMORY DEVICE AND METHOD HAVING A SHARED POWER BANK AND PROCESSOR-BASED SYSTEMS USING SAME A word line driver system that utilizes a voltage selection circuit to supply one of several voltages to an output node coupled to a plurality of word line control circuits. Each word line control circuit is coupled to a respective word line in an array of non-volatile ... | 05/12/2011 |
| 20110103154 | LOCAL SELF-BOOSTING METHOD OF FLASH MEMORY DEVICE AND PROGRAM METHOD USING THE SAME Provided is a local self-boosting method of a flash memory device including at least one string having memory cells respectively connected to wordlines. The local self-boosting method includes forming a potential well at a channel of the string and forming potential wal... | 05/05/2011 |
| 20110103153 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DRIVING SAME According to one embodiment, a nonvolatile semiconductor memory device includes a substrate, a stacked body, a semiconductor pillar, a charge storage film, and a drive circuit. The stacked body is provided on the substrate. The stacked body includes a plurality of insul... | 05/05/2011 |
| 20110096602 | NONVOLATILE MEMORY DEVICES OPERABLE USING NEGATIVE BIAS VOLTAGES AND RELATED METHODS OF OPERATION A nonvolatile memory device includes a first address decoder and a second address decoder. The first address decoder includes a plurality of transistors disposed in a first well, and the second address decoder includes a plurality of transistors disposed in a second wel... | 04/28/2011 |
| 20110090743 | Sub Volt Flash Memory System Various circuits include MOS transistors that have a bulk voltage terminal for receiving a bulk voltage that is different from a supply voltage and ground. The bulk voltage may be selectively set so that some MOS transistors have a bulk voltage set to the supply voltage... | 04/21/2011 |
