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Actor Marlon Brando has four patents, all named "Drumhead tensioning device and method."
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| Application No. | Application Title | Issue Date |
| 20120127799 | WRITE-PRECOMPENSATION AND VARIABLE WRITE BACKOFF A technique for writing data is disclosed. The technique includes estimating an amount of additional voltage on a victim cell of a solid-state storage device caused by writing to one or more other cells in the solid-state storage device, determining a modified write val... | 05/24/2012 |
| 20120127802 | NON-VOLATILE MEMORY DEVICE, METHOD OF OPERATING THE SAME, AND ELECTRONIC DEVICE HAVING THE SAME In one embodiment, the method includes receiving an operation command, detecting a noise level of a common source line, and adjusting a number of times to perform an operation on a memory cell in response to the operation command based on the detected noise level.... | 05/24/2012 |
| 20120127798 | METHOD AND APPARATUS FOR SHARING INTERNAL POWER SUPPLIES IN INTEGRATED CIRCUIT DEVICES A method, system and apparatus for sharing internal power supplies in integrated circuit devices is described. A multiple device integrated circuit 200 including multiple integrated circuits 202-205 each having internal power supplies is contained i... | 05/24/2012 |
| 20120106255 | VOLTAGE GENERATION CIRCUIT WHICH IS CAPABLE OF REDUCING CIRCUIT AREA According to one embodiment, a voltage generation circuit includes a first boost circuit, a first output circuit, a rectifying circuit, a second output circuit, and a detection circuit. The first boost circuit outputs a first voltage in first and second operation modes.... | 05/03/2012 |
| 20120106249 | PROGRAMMING ERROR CORRECTION CODE INTO A SOLID STATE MEMORY DEVICE WITH VARYING BITS PER CELL Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bi... | 05/03/2012 |
| 20120106259 | Adaptive Control of Programming Currents for Memory Cells A method includes performing a first programming operation on a plurality of memory cells in a same programming cycle; and performing a verification operation on the plurality of memory cells to find failed memory cells in the plurality of memory cells, wherein the fail... | 05/03/2012 |
| 20120106254 | MEMORY SYSTEM According to one embodiment, a memory system includes a NAND flash memory, a first unit, and an second unit. Memory cells capable of holding data and management data as a first control signal. Memory cells are arranged in a matrix in the NAND flash memory. The first uni... | 05/03/2012 |
| 20120106251 | FLASH MEMORY DEVICE CONFIGURED TO SWITCH WORDLINE AND INITIALIZATION VOLTAGES Provided is a flash memory device including a wordline voltage generating unit, a switch unit, a row decoder and a control circuit. The wordline voltage generating unit generates at least one wordline voltage for read operations of a multi-level cell in the flash memory... | 05/03/2012 |
| 20120106256 | ELECTRONIC CIRCUIT WITH A FLOATING GATE TRANSISTOR AND A METHOD FOR DEACTIVATING A FLOATING GATE TRANSISTOR TEMPORARILY An electronic circuit includes a floating gate transistor with a floating gate capacitor. The floating gate transistor can be programmed to be in an ON or an OFF state by charging the floating gate capacitor. The circuit further includes a deactivation capacitor adapted... | 05/03/2012 |
| 20120106262 | PROGRAMMING METHOD FOR NONVOLATILE MEMORY APPARATUS Provided is a method for programming a nonvolatile memory apparatus which includes a bit line selector coupled to first and second bit lines and a page buffer including a main data transmission switch coupled to the bit line selector, a first latch coupled to the main d... | 05/03/2012 |
| 20120106247 | FLASH MEMORY DEVICE INCLUDING FLAG CELLS AND METHOD OF PROGRAMMING THE SAME Provided is a flash memory device and a method of programming the same. The flash memory device includes a memory cell array, a first judgment circuit and a second judgment circuit. The memory cell array includes multiple main cells and multiple flag cells. The first ju... | 05/03/2012 |
| 20120081957 | FLASH MEMORY DEVICE AND WORDLINE VOLTAGE GENERATING METHOD THEREOF A word line voltage generating method of a flash memory which includes generating a program voltage using a positive voltage generator; generating a plurality of negative program verification voltages corresponding to a plurality of negative data states using a negative... | 04/05/2012 |
| 20120081967 | METHOD AND SYSTEM FOR PROGRAMMING NON-VOLATILE MEMORY CELLS BASED ON PROGRAMMING OF PROXIMATE MEMORY CELLS A multi-level non-volatile memory device programs cells in each row in a manner that takes into account the coupling from the programming of cells that are proximate the row to be programmed. In one example of the invention, after the row has been programmed, the proxim... | 04/05/2012 |
| 20120081968 | N WELL IMPLANTS TO SEPARATE BLOCKS IN A FLASH MEMORY DEVICE A semiconductor memory device that has an isolated area formed from one conductivity and formed in part by a buried layer of a second conductivity that is implanted in a substrate. The walls of the isolated area are formed by implants that are formed from the second con... | 04/05/2012 |
| 20120081972 | MEMORY ARRAYS AND METHODS OF OPERATING MEMORY Apparatus and methods for determining pass/fail condition of memories are disclosed. In at least one embodiment, a set of common lines, one for each rank of page buffers corresponding to a page, determine the pass/fail status of all connected memory cells, and the pass/... | 04/05/2012 |
| 20120081959 | MEMORY SYSTEM AND PROGRAMMING METHOD THEREOF Provided are a non-volatile memory system and a programming method thereof. The programming method of the non-volatile memory system includes adjusting a program-verify-voltage of a selected memory cell referring to program data to be written in an interfering cell conf... | 04/05/2012 |
| 20120081966 | COMBINED EEPROM/FLASH NON-VOLATILE MEMORY CIRCUIT A non-volatile memory circuit includes memory rows and supporting circuits coupled to the memory rows, where at least one of the memory rows include at least one Electrically Erasable Programmable Read-Only Memory (EEPROM) memory element and at least one Flash memory el... | 04/05/2012 |
| 20120069657 | MEMORY DEVICE AND SELF INTERLEAVING METHOD THEREOF A memory device includes a memory cell array, a self interleaver configured to interleave and load data on the fly into a buffer circuit using an interleaving scheme, and a control logic configured to control programming of the interleaved data in the memory cell array.... | 03/22/2012 |
| 20120069664 | FLASH MEMORY SYSTEM AND WORD LINE INTERLEAVING METHOD THEREOF Provided are a flash memory system and a word line interleaving method thereof. The flash memory system includes a memory cell array, and a word line interleaving logic. The memory cell array is connected to a plurality of word lines. The word line (WL) interleaving log... | 03/22/2012 |
| 20120069665 | Memory Device With Vertically Embedded Non Flash Non Volatile Memory For Emulation Of Nand Flash Memory A system and a method for emulating a NAND memory system are disclosed. In the method, a command associated with a NAND memory is received. After receipt of the command, a vertically configured non-volatile memory array is accessed based on the command. In the system, a... | 03/22/2012 |
| 20120069680 | NAND WITH BACK BIASED OPERATION Methods of programming, reading and erasing memory cells are disclosed. In at least one embodiment, program, sense, and erase operations in a memory are performed with back biased operation, such as to improve high voltage device isolation and cutoff in string drivers a... | 03/22/2012 |
| 20120069681 | SEMICONDUCTOR STORAGE DEVICE According to one embodiment, a semiconductor storage device includes a cell array, a controller, and a voltage generator. The cell array includes cells. Each of the cells holds data “0” or “1”. The controller counts the number of times N of sequentially writing ... | 03/22/2012 |
| 20120069668 | SEMICONDUCTOR DEVICE According to one embodiment, a semiconductor storage device includes a transistor, a first node, a first capacitor, a first switch, and a second switch. One end of the transistor is connected to a first voltage source supplying a first voltage. The first node is charged... | 03/22/2012 |
| 20120069673 | METHOD AND DEVICE FOR PROGRAMMING DATA INTO NON-VOLATILE MEMORIES A device includes a non-volatile memory and a control unit, wherein the control unit is configured to change over programming of data of the non-volatile memory from a first programming mode to a second, different programming mode based on the occurrence of a control si... | 03/22/2012 |
| 20120069683 | SEMICONDUCTOR STORAGE DEVICE According to one embodiment, a semiconductor storage device includes a cell array, an even line, an odd line, and sense amplifiers. The cell array includes memory cells holding data. The even line connects to the memory cells. The odd line connects to the memory cells. ... | 03/22/2012 |
| 20120069670 | Semiconductor Integrated Circuit Device for Driving Liquid Crystal Display The present invention realizes a semiconductor integrated circuit device for driving liquid crystal (liquid crystal control driver IC) capable of easily setting drive conditions and the like according to specifications of a liquid crystal display to be used. An electric... | 03/22/2012 |
| 20120069671 | MEMORY AND OPERATION METHOD THEREFOR An operation method for a memory device having a plurality of memory cells includes: reading the plurality of memory cells by a first word line voltage to get a first number of a first logic state; reading the plurality of memory cells by a second word line voltage to g... | 03/22/2012 |
| 20120069669 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF CONTROLLING AND MANUFACTURING THE SAME A nonvolatile semiconductor storage device is disclosed. The device includes a cell group having a first memory cell and a second memory cell located first directionally adjacent to the first memory cell, and a programming circuit. The first memory cell is used for data... | 03/22/2012 |
| 20120069667 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE CAPABLE OF SPEEDING UP DATA WRITE According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control circuit. The memory cell array having a plurality of memory cells is connected to a plurality of word lines stacked on a semiconductor substrate, and the me... | 03/22/2012 |
| 20120051147 | AREA SAVING ELECTRICALLY-ERASABLE-PROGRAMMABLE READ-ONLY MEMORY (EEPROM) ARRAY An area saving electrically-erasable-programmable read-only memory (EEPROM) array, having: a plurality of parallel bit lines, a plurality of parallel word lines, and a plurality of parallel common source lines. The bit lines are classified into a plurality of bit line g... | 03/01/2012 |
| 20120051146 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF MEMORIZING MULTIVALUED DATA In a memory cell array, a plurality of memory cells connected to word lines and bit lines are arranged in a matrix. A data storage circuit is connected to the bit lines and stores write data. The data storage circuit includes at least one static latch circuit and a plur... | 03/01/2012 |
| 20120051142 | Soft Program Method and Computer Redable Medium Thereof A soft program method is provided for recovering memory cells of a memory array. In an embodiment, the method includes the following steps. Memory blocks of the memory array are soft programmed with first bias voltage. A selected memory unit within a selected memory blo... | 03/01/2012 |
| 20120051145 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME A memory device includes a block switch for transferring operating voltages, supplied to global lines, to local lines coupled to a memory cell array in response to the voltage level of a block selection signal and a negative voltage transfer circuit for transferring a n... | 03/01/2012 |
| 20120051140 | RAM memory device with NAND type interface A random access memory device is disclosed having an interface that is compatible with a NAND FLASH memory device such that the device can be operated with a standard NAND memory device's controller device. This memory device is can store data internally using any rando... | 03/01/2012 |
| 20120051141 | MULTI-BIT FLASH MEMORY DEVICES AND METHODS OF PROGRAMMING AND ERASING THE SAME A non-volatile memory device includes an array of non-volatile memory cells configured to support single bit and multi-bit programming states. A control circuit is provided, which is configured to program a first page of non-volatile memory cells in the array as M-bit c... | 03/01/2012 |
| 20120044763 | Non-Volatile Memory and Semiconductor Device There is provided a non-volatile memory which enables high accuracy threshold control in a writing operation. In the present invention, a drain voltage and a drain current of a memory transistor are controlled to carry out a writing operation of a hot electron injection... | 02/23/2012 |
| 20120044766 | SEMICONDUCTOR MEMORY DEVICE WITH A STACKED GATE INCLUDING A CHARGE STORAGE LAYER AND A CONTROL GATE AND METHOD OF CONTROLLING THE SAME A semiconductor memory device includes a transfer circuit and a control circuit. The transfer circuit which includes a p-type MOS transistor with a source to which is applied a first voltage and an n-type MOS transistor to whose gate the drain of the p-type MOS transist... | 02/23/2012 |
| 20120044769 | MULTI-PASS PROGRAMMING IN A MEMORY DEVICE A method for programming a memory device, a memory device, and a memory system are provided. According to at least one such method, a first programming pass generates a plurality of first programming pulses to increase the threshold voltages of target memory cells to ei... | 02/23/2012 |
| 20120044767 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME A non-volatile memory device includes a plurality of unit cells. Each unit cell includes lower and upper electrodes over a substrate, a conductive organic material layer between the lower and the upper electrodes, and a nanocrystal layer located within the conductive or... | 02/23/2012 |
| 20120044772 | NON-VOLATILE MEMORY DEVICE, SYSTEM, AND CELL ARRAY A non-volatile memory cell array, comprising sector selection transistors controlled by a voltage applied to sector selection lines, first through fourth memory cells connected in series to the sector selection transistors, a first common source line connected between t... | 02/23/2012 |
