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| Application No. | Application Title | Issue Date |
| 20130128669 | OPERATION FOR NON-VOLATILE STORAGE SYSTEM WITH SHARED BIT LINES A non-volatile storage system is disclosed that includes pairs of NAND strings (or other groupings of memory cells) in the same block being connected to and sharing a common bit line. To operate the system, two selection lines are used so that the NAND strings (or other... | 05/23/2013 |
| 20130121079 | NOR FLAH MEMORY CELL AND STRUCTURE THEREOF The present invention provides a NOR flash memory cell. The NOR flash memory cell includes a first transistor, a second transistor and at least one third transistor. The first transistor has a control terminal, a first terminal and a second terminal. The control termina... | 05/16/2013 |
| 20130114341 | Method and Apparatus for Indicating Bad Memory Areas Regardless of data values stored on data memory cells, all read operations on the data memory cells are disallowed. For example, current flow is disallowed through a string of the data memory cells and one or more select line memory cells. The particular select value st... | 05/09/2013 |
| 20130114342 | DEFECTIVE WORD LINE DETECTION Methods and non-volatile storage systems are provided for detecting defects in word lines. A “broken” word line defect may be detected. Information may be maintained as to which storage elements were intended to be programmed to a tracked state. Then, after programm... | 05/09/2013 |
| 20130107628 | Selective Word Line Erase In 3D Non-Volatile Memory An erase process for a 3D stacked memory device allows a portion of a block of memory cells to be erased. In one approach, in a U-shaped NAND string configuration, memory cells in the drain- or source-side columns are erased. In another approach, such as in a U-shaped o... | 05/02/2013 |
| 20130107627 | BACK-BIASING WORD LINE SWITCH TRANSISTORS Back biasing word line switch transistors is disclosed. One embodiment includes word line switch transistors that are in a well in a substrate. A memory array having non-volatile storage devices may be in a separate well in the substrate. The well of the word line switc... | 05/02/2013 |
| 20130107629 | NONVOLATILE MEMORY DEVICES AND OPERATING METHODS THEREOF According to example embodiments of inventive concepts, a nonvolatile memory device includes a memory cell array including a plurality of memory cells; a word line driver configured to at least one of select and unselect a plurality of word lines connected with the plur... | 05/02/2013 |
| 20130107626 | METHODS FOR SEGMENTED PROGRAMMING AND MEMORY DEVICES Methods for segmented programming, program verify, and memory devices are disclosed. One such method for programming includes biasing memory cells with a programming voltage and program verifying the memory cells with a plurality of ramped voltage signal segments, where... | 05/02/2013 |
| 20130094294 | NONVOLATILE MEMORY DEVICE, PROGRAMMING METHOD OF NONVOLATILE MEMORY DEVICE AND MEMORY SYSTEM INCLUDING NONVOLATILE MEMORY DEVICE Disclosed are a program method and a nonvolatile memory device. The method includes receiving program data to be programmed in memory cells; reading the memory cells to judge an erase state and at least one program state; performing a state read operation in which the a... | 04/18/2013 |
| 20130088918 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE A non-volatile semiconductor memory device includes a semiconductor layer of a first conductivity type, and a plurality of wells of a second conductivity type formed on the first semiconductor layer, the wells being arranged in a first direction. A memory block is arran... | 04/11/2013 |
| 20130088921 | OPERATING METHOD OF NONVOLATILE MEMORY AND METHOD OF CONTROLLING NONVOLATILE MEMORY An operating method of a nonvolatile memory, which includes a plurality of cell strings, each cell string having a plurality of memory cells and a string selection transistor stacked on a substrate, includes detecting threshold voltages of the string selection transisto... | 04/11/2013 |
| 20130088920 | LOW VOLTAGE PROGRAMMING IN NAND FLASH WITH TWO STAGE SOURCE SIDE BIAS A memory device includes a plurality of memory cells arranged in series in the semiconductor body, such as a NAND string, having a plurality of word lines. A selected memory cell is programmed by hot carrier injection. The program operation is based on metering a flow o... | 04/11/2013 |
| 20130083603 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE One embodiment includes a write control unit that performs a first write operation with respect to a first threshold distribution, a first verify operation on the first threshold distribution, and a second write operation on the basis of a result of the first verify ope... | 04/04/2013 |
| 20130083602 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE According to one embodiment, a write control unit performs a condition verify operation of searching for a low level region and a high level region of memory cells, and sets a write voltage of the low level region and the high level region in common and individually set... | 04/04/2013 |
| 20130083601 | VERTICAL NAND MEMORY A vertical NAND structure includes one or more mid-string devices having at least two functional modes. In the first mode, the one or more mid-string devices couple the bodies of stacks of NAND memory cells to the substrate for erase operations. In the second mode, the ... | 04/04/2013 |
| 20130077404 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE A nonvolatile semiconductor memory device according to one embodiment includes: memory cells; word lines connected to the memory cells; and a control circuit configured to control a data read operation. When controlling the data read operation, the control circuit appli... | 03/28/2013 |
| 20130070531 | SUBSTRATE BIAS DURING PROGRAM OF NON-VOLATILE STORAGE A programming technique which reduces program disturb in a non-volatile storage system is disclosed. A positive voltage may be applied to a substrate (e.g., p-well) during programming. Biasing the substrate may improve boosting of channels of unselected NAND strings, wh... | 03/21/2013 |
| 20130070530 | HIGH ENDURANCE NON-VOLATILE STORAGE A non-volatile storage system is disclosed that includes non-volatile memory cells designed for high endurance and lower retention than other non-volatile memory cells.... | 03/21/2013 |
| 20130051147 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE A nonvolatile semiconductor memory device includes bit lines, word lines, NAND strings, source lines, first and second select gate transistors, and a controller. After giving a first potential to the second select gate transistors, the controller gives a second potentia... | 02/28/2013 |
| 20130044545 | NON-VOLATILE MEMORY DEVICE HAVING VERTICAL STRUCTURE AND METHOD OF OPERATING THE SAME A non-volatile memory device having a vertical structure includes a NAND string having a vertical structure. The NAND string includes a plurality of memory cells, and at least one pair of first selection transistors arranged to be adjacent to a first end of the pluralit... | 02/21/2013 |
| 20130044544 | NONVOLATILE MEMORY DEVICE According to one embodiment, a nonvolatile memory device includes a circuit and a memory cell. The circuit outputs a program voltage. The memory cell is programmed data by being applied the program voltage. The circuit outputs the program voltage so as to satisfy the fo... | 02/21/2013 |
| 20130028021 | Simultaneous Sensing of Multiple Wordlines and Detection of NAND Failures Techniques for a post-write read are presented. In an exemplary embodiment, a combined simultaneous sensing of multiple word lines is used in order to identify a problem in one or more of these word lines. That is, sensing voltages are concurrently applied to the contro... | 01/31/2013 |
| 20130021847 | NONVOLATILE MEMORY DEVICE AND RELATED PROGRAMMING METHOD A nonvolatile memory device comprises a memory cell array comprising a plurality of memory blocks each divided into a plurality of regions, and a control logic component. The control logic component selects a memory block to be programmed based on program/erase cycles o... | 01/24/2013 |
| 20130021848 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF DATA WRITE THEREIN A memory cell comprises a first semiconductor layer, and a first conductive layer. The first semiconductor layer extends in a perpendicular direction with respect to a semiconductor substrate. The first conductive layer sandwiches a charge storage layer with the first s... | 01/24/2013 |
| 20130003458 | NAND ARCHITECTURE MEMORY WITH VOLTAGE SENSING A NAND architecture non-volatile memory voltage sensing data read/verify process and sense amplifier has been described that senses data in floating gate or floating node field effect transistor memory cells using a voltage sensing data read/verify process. The voltage ... | 01/03/2013 |
| 20130007349 | SMART BRIDGE FOR MEMORY CORE An apparatus includes a first semiconductor device including a NAND flash memory core. The apparatus also includes a second semiconductor device including periphery circuitry associated with the NAND flash memory core.... | 01/03/2013 |
| 20130003461 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF REDUCING CHIP SIZE According to one embodiment, a first well of the first conductivity type which is formed in a substrate. a second well of a second conductivity type which is formed in the first well. The plurality of memory cells, the plurality of first bit line select transistors, and... | 01/03/2013 |
| 20130003459 | Read Error Recovery for Solid-State Memory Based on Cumulative Background Charges A read error is determined that affects a page of solid-state, non-volatile memory. The page is associated with a selected word line that crosses a plurality of NAND strings coupled to respective grounds and bit lines. Word lines of the memory are ordered from a lower e... | 01/03/2013 |
| 20120327715 | NONVOLATILE MEMORY DEVICES HAVING VERTICALLY INTEGRATED NONVOLATILE MEMORY CELL SUB-STRINGS THEREIN Methods of forming nonvolatile memory devices according to embodiments of the invention include techniques to form highly integrated vertical stacks of nonvolatile memory cells. These vertical stacks of memory cells can utilize dummy memory cells to compensate for proce... | 12/27/2012 |
| 20120327714 | Memory Architecture of 3D Array With Diode in Memory String Various embodiments are directed to 3D memory arrays that lack a select line and devices controlled by the select line between one of the source line and the bit line, and the memory cells. Diodes between the other of source line and the bit line, and the memory cells p... | 12/27/2012 |
| 20120327713 | IN-FIELD BLOCK RETIRING Memory devices and methods are disclosed, including a method involving erasing a block of memory cells. After erasing the block, and before subsequent programming of the block, a number of bad strings in the block are determined based on charge accumulation on select ga... | 12/27/2012 |
| 20120307561 | NON-VOLATILE MEMORY DEVICE AND METHOD CONTROLLING DUMMY WORD LINE VOLTAGE ACCORDING TO LOCATION OF SELECTED WORD LINE A non-volatile memory device includes access circuitry that selects a word line during an operation, applies a selected word line voltage to the selected word line, applies a non-selected word line voltage to non-selected word lines among the word lines, and applies a d... | 12/06/2012 |
| 20120300550 | Ramping Pass Voltage To Enhance Channel Boost In Memory Device, With Optional Temperature Compensation In a non-volatile storage system, one or more substrate channel regions for an unselected NAND string are boosted during programming to inhibit program disturb. A voltage applied to one or more unselected word lines associated with at least a first channel region is inc... | 11/29/2012 |
| 20120300551 | NON-VOLATILE MEMORY CELL HEALING Embodiments of the present disclosure provide methods, devices, modules, and systems for healing non-volatile memory cells. One method includes biasing a first select gate transistor coupled to a string of memory cells at a first voltage, biasing a second select gate tr... | 11/29/2012 |
| 20120287716 | Using Channel-To-Channel Coupling To Compensate Floating Gate-To-Floating Gate Coupling In Programming Of Non-Volatile Memory In a non-volatile storage system, during a verify operation, a verify voltage of a currently-sensed target data state is applied to a selected word line. A higher, nominal bit line voltage is used for the storage elements which have the currently-sensed target data stat... | 11/15/2012 |
| 20120281475 | NAND FLASH MEMORY DEVICE AND METHOD OF MAKING SAME An integrated circuit includes a NAND string including a string selection transistor SST and a ground selection transistor GST disposed at either end of series-connected memory storage cells MC. Each of the memory storage cells is a memory transistor having a floating g... | 11/08/2012 |
| 20120275225 | Variable Resistance Switch Suitable for Supplying High Voltage to Drive Load A circuit for supplying a high voltage to load is described. An example of such a circuit could be used in the peripheral circuitry of a non-volatile memory device for supplying a program voltage from a charge pump to a selected word line. The circuit includes a charge ... | 11/01/2012 |
| 20120275227 | PHOTOSENSITIVE COMPOSITION AND COMPOUND FOR USE IN THE PHOTOSENESITIVE COMPOSITION A programming method and memory structure for preventing punch-through in a short channel source-side select gate structure includes adjusting voltages on the selected and unselected bitlines, and the program, pass, and select gate voltages.... | 11/01/2012 |
| 20120275226 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE CAPABLE OF REDUCING POWER CONSUMPTION According to one embodiment, a nonvolatile semiconductor memory device includes an electrically rewritable nonvolatile memory, a grounding pad, a first power supply pad, a second power supply pad, a voltage reduction circuit, and a first pump circuit. A first power supp... | 11/01/2012 |
| 20120250414 | REDUCING NEIGHBOR READ DISTURB Methods and devices for sensing non-volatile storage devices in a way that reduces read disturb are disclosed. Techniques are used to reduce read disturb on memory cells that are neighbors to selected memory cells. For example, on a NAND string, the memory cells that ar... | 10/04/2012 |
