Class 365/185.15 - Weak inversion injection

Subclass of Class 365 - Static information storage and retrieval
Definition: Subject matter under 185.14 wherein use of an auxiliary
No. of applications: 42
Last issue date: 05/24/2012

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Application No.	Application Title	Issue Date
20120127796	RETENTION IN NVM WITH TOP OR BOTTOM INJECTION Retention of charges in a nonvolatile memory (NVM) cell having a nitride-based injector (such as SiN, SIRN, SiON) for facilitating injection of holes into a charge-storage layer (for NROM, nitride) of a charge-storage stack (for NROM, ONO) may be improved by providing a...	05/24/2012
20120081962	LOW VOLTAGE PROGRAMMING IN NAND FLASH A memory device includes a plurality of memory cells arranged in series in the semiconductor body, such as a NAND string, having a plurality of word lines. A selected memory cell is programmed by hot carrier injection. The program operation is based on metering a flow o...	04/05/2012
20110310669	Logic-Based Multiple Time Programming Memory Cell A non-volatile memory system includes one or more non-volatile memory cells. Each non-volatile memory cell comprises a floating gate, a coupling device, a first floating gate transistor, and a second floating gate transistor. The coupling device is located in a first co...	12/22/2011
20110305088	HOT CARRIER PROGRAMMING IN NAND FLASH A memory device includes a plurality of memory cells arranged in series in the semiconductor body, such as a NAND string, having a plurality of word lines. A selected memory cell is programmed by hot carrier injection using a boosted channel potential to establish the h...	12/15/2011
20110235419	NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE In a split gate MONOS memory which carries out rewrite by hot carrier injection, retention characteristics are improved. A select gate electrode of a memory cell is connected to a select gate line, and a memory gate electrode is connected to a memory gate line. A drain ...	09/29/2011
20110216595	NAND FLASH MEMORY OF USING COMMON P-WELL AND METHOD OF OPERATING THE SAME A flash memory using hot carrier injection and a method of operating the same are provided. A plurality of strings constituting a page are formed on a single p-well and share the p-well. During a program operation, a string selection transistor is turned off, and electr...	09/08/2011
20110205799	OPERATION METHOD OF MEMORY DEVICE A method for operating a memory device is provided. In accordance with the method, the charges are stored in a source storage region, a drain storage region, and a channel storage region of a charge storage layer which respectively correspond to a source, a drain, and a...	08/25/2011
20110176365	TWO TERMINAL PROGRAMMABLE HOT CHANNEL ELECTRON NON-VOLATILE MEMORY A programmable two terminal non-volatile device uses a floating gate that can be programmed by a hot electron injection induced by a potential between a source and drain. The floating gate layer can also function as a FET gate for other circuits in an integrated circuit...	07/21/2011
20110134694	High Voltage Generation And Control In Source-Side Injection Programming Of Non-Volatile Memory Non-volatile memory is programmed using source side hot electron injection. To generate a high voltage bit line for programming, the bit line corresponding to a selected memory cell is charged to a first level using a first low voltage. A second low voltage is applied t...	06/09/2011
20110116317	PROGRAM AND ERASE METHODS WITH SUBSTRATE TRANSIENT HOT CARRIER INJECTIONS IN A NON-VOLATILE MEMORY The present invention describes a uniform program method and a uniform erase method of a charge trapping memory by employing a substrate transient hot electron technique for programming, and a substrate transient hot hole technique for erasing, which emulate an FN tunne...	05/19/2011
20110116316	NONVOLATILE RANDOM ACCESS MEMORY A nonvolatile random access memory that can be mounted on a substrate during a standard CMOS process. A memory cell comprises: a first MIS transistor including a first semiconductor layer of a first conductivity type in an electrically floating state, first drain and so...	05/19/2011
20110063914	NONVOLATILE SEMICONDUCTOR MEMORY DEVICE A nonvolatile semiconductor memory device includes: a memory unit; and a control unit. The memory unit includes: a multilayer structure including electrode films and interelectrode insulating films alternately stacked; a semiconductor pillar piercing the multilayer stru...	03/17/2011
20100271878	INJECTION METHOD WITH SCHOTTKY SOURCE/DRAIN An injection method for non-volatile memory cells with a Schottky source and drain is described. Carrier injection efficiency is controlled by an interface characteristic of silicide and silicon. A Schottky barrier is modified by controlling an overlap of a gate and a s...	10/28/2010
20100259985	Trap-charge non-volatile switch connector for programmable logic A nonvolatile trap charge storage cell selects a logic interconnect transistor uses in programmable logic applications, such as FPGA. The nonvolatile trap charge element is an insulator located under a control gate and above an oxide on the surface of a semiconductor su...	10/14/2010
20100259986	Trap-charge non-volatile switch connector for programmable logic A nonvolatile trap charge storage cell selects a logic interconnect transistor uses in programmable logic applications, such as FPGA. The nonvolatile trap charge element is an insulator located under a control gate and above an oxide on the surface of a semiconductor su...	10/14/2010
20100259984	ERASE METHOD OF NONVOLATILE SEMICONDUCTOR MEMORY DEVICE An erase method of a nonvolatile semiconductor memory device including a semiconductor substrate with diffusion regions spaced from each other, a first insulating layer formed on the semiconductor substrate, a first gate electrode formed in a first area on the first ins...	10/14/2010
20100246267	Systems and Methods Of Providing Programmable Voltage And Current Reference Devices The present invention describes systems and methods to for providing stable and programmable voltage and current reference devices. An exemplary embodiment of the present invention provides a voltage reference device having a first floating-gate transistor with a first ...	09/30/2010
20100202205	SEMICONDUCTOR DEVICE The degree of integration and the number of rewriting of a semiconductor device having a nonvolatile memory element are improved. A first MONOS nonvolatile-memory-element and a second MONOS nonvolatile-memory-element having a large gate width compared with the first MON...	08/12/2010
20100157669	Floating Gate Inverter Type Memory Cell And Array A non-volatile memory (NVM) cell and array includes a control capacitor, tunneling capacitor, CMOS inverter and output circuit. The CMOS inverter includes PMOS and NMOS inverter transistors. The control capacitor, tunneling capacitor and PMOS and NMOS inverter transisto...	06/24/2010
20100142273	PROGRAMMING METHODS FOR MULTI-LEVEL MEMORY DEVICES A method is provided for programming a memory cell. The memory cell is fabricated on a substrate and comprises a source region, a drain region, a floating gate, and a control gate. The memory cell has a threshold voltage selectively configurable into one of at least thr...	06/10/2010
20100135080	FABRICATION METHOD AND STRUCTURE OF SEMICONDUCTOR NON-VOLATILE MEMORY DEVICE A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film composed of a...	06/03/2010
20100074005	EEPROM EMULATION IN FLASH DEVICE Flash memory systems and methodologies are provided herein for providing byte alterability in a flash device. Logical cell mapping is changed from using a single physical memory cell to using two adjacent physical cells as a logical cell for emulating byte alterability....	03/25/2010
20100074013	Semiconductor Device and Method of Fabricating the Same A method of fabricating a semiconductor device and a flash memory device are provided. The method of fabricating the semiconductor device includes: forming a nitride film on a semiconductor substrate; forming a sacrificial vertical structure on the nitride film; forming...	03/25/2010
20100074006	DYNAMIC ERASE STATE IN FLASH DEVICE Flash memory systems and methodologies are provided herein for facilitating a single logical cell erasure and dynamic erase state. The single logical cell erasure can be accomplished on a basis of a single program and erase entity which is a combination of neighboring d...	03/25/2010
20100074004	HIGH VT STATE USED AS ERASE CONDITION IN TRAP BASED NOR FLASH CELL DESIGN Flash memory systems and methodologies are provided herein for using a high voltage state as an erase condition in a flash device. Logical cell mapping is changed from using a single physical memory cell to using two adjacent physical cells as a single logical cell, the...	03/25/2010
20090323415	FLASH MEMORY ARRAY SYSTEM INCLUDING A TOP GATE MEMORY CELL A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. Th...	12/31/2009
20090316484	SEMICONDUCTOR MEMORY DEVICE, METHOD OF DRIVING THE SAME AND METHOD OF MANUFACTURING THE SAME Disclosed is a semiconductor storage device comprising a semiconductor substrate, a first and a second impurity diffusion layer formed in the semiconductor substrate, a gate insulating film formed on the semiconductor substrate, and a first gate electrode formed on the ...	12/24/2009
20090296474	PROGRAM AND ERASE METHODS WITH SUBSTRATE TRANSIENT HOT CARRIER INJECTIONS IN A NON-VOLATILE MEMORY The present invention describes a uniform program method and a uniform erase method of a charge trapping memory by employing a substrate transient hot electron technique for programming, and a substrate transient hot hole technique for erasing, which emulate an FN tunne...	12/03/2009
20090168531	METHOD FOR PROGRAMMING A MEMORY STRUCTURE A memory structure includes a first memory cell and a second memory cell located at an identical bit line and adjacent to the first memory cell. Each memory cell includes a substrate, a source, a drain, a charge storage device, and a gate. A method for programming the m...	07/02/2009
20090154246	PROGRAMMING IN MEMORY DEVICES USING SOURCE BITLINE VOLTAGE BIAS Systems and methods that facilitate improved programming memory cells in a nonvolatile memory (e.g., flash memory) are presented. An optimized voltage component can facilitate supplying respective voltages to a source, drain, and gate associated with a memory cell durin...	06/18/2009
20090147577	NON-VOLATILE SEMICONDUCTOR LATCH USING HOT-ELECTRON INJECTION DEVICES The invention concerns semiconductor latches capable of memorizing any programmed information even after power supply has been removed. Used is a 0.6 m BiCMOS EPROM process but it is applicable in any other process having hot electron injection devices like EPROM, Flash...	06/11/2009
20090046508	Programming methods for multi-level flash EEPROMs A method is provided for programming a memory cell of an electrically erasable programmable read only memory. The memory cell is fabricated on a substrate and comprises a source region, a drain region, a floating gate, and a control gate. The memory cell has a threshold...	02/19/2009
20090027967	NON-VOLATILE MEMORY DEVICE PROGRAMMING SELECTION TRANSISTOR AND METHOD OF PROGRAMMING THE SAME A memory system includes a flash memory device and a memory controller for controlling the flash memory device. The flash memory device includes a cell string and a selection transistor connected in series to the cell string. The cell string includes multiple series-con...	01/29/2009
20080304320	MEMORY CELL AND METHOD OF PROGRAMMING THE SAME A method of programming a memory cell is described. The memory cell includes a gate with a charge trapping layer isolated from a substrate for storing data with a first region and a second region separated from the first region. The method of programming the memory cell...	12/11/2008
20080273387	Nonvolatile Semiconductor Storage Device and Method for Writing Therein A hot electron (BBHE) is generated close to a drain by tunneling between bands, and bit data writing is performed by injecting the hot electron into a charge storage layer. When Vg is a gate voltage, Vsub is a cell well voltage, Vs is a source voltage and Vd is a drain ...	11/06/2008
20080239817	Nonvolatile semiconductor memory device and method of erasing and programming the same A nonvolatile semiconductor memory device includes a semiconductor substrate having a source, a drain, and a channel region between the source and the drain. The channel region has a first end portion near the drain, a second end portion near the source, and a middle po...	10/02/2008
20080181006	METHOD OF PROGRAMMING MEMORY CELL A method of programming a memory cell is described. First, a first programming operation is performed to inject electrons into a nitride layer adjacent to a side of a drain. The first programming operation includes applying a first gate voltage to a gate, applying a fir...	07/31/2008
20080158965	OPERATING METHOD OF NON-VOLATILE MEMORY A non-volatile memory including a substrate, a select gate, two floating gates, a control gate, and a doped region is described. The select gate is disposed on the substrate. The two floating gates are disposed on both sides of the select gate, and the top surface of th...	07/03/2008
20080151627	METHOD OF LOW VOLTAGE PROGRAMMING OF NON-VOLATILE MEMORY CELLS A low voltage method of programming a selected non-volatile memory cell in a memory array having a gate node coupled to a wordline WL(n) and a drain node connected to a selected bitline by injecting hot carriers from a drain region of an injecting memory cell having a g...	06/26/2008
20080151629	SEMICONDUCTOR DEVICE The degree of integration and the number of rewriting of a semiconductor device having a nonvolatile memory element are improved. A first MONOS nonvolatile-memory-element and a second MONOS nonvolatile-memory-element having a large gate width compared with the first MON...	06/26/2008

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Class 365/185.15 - Weak inversion injection