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"I hate what they've done to my child...I would never let my own children watch it. "
Vladimir Zworykin, television pioneer ; Talking about an invention in which he played a critical role.
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| Application No. | Application Title | Issue Date |
| 20120051129 | MEMORY DEVICE HAVING THREE-DIMENSIONAL GATE STRUCTURE Subject matter disclosed herein relates to a memory device, and more particularly to a nonvolatile memory device having a recess structure and methods of fabricating same.... | 03/01/2012 |
| 20110255335 | CHARGE TRAP MEMORY HAVING LIMITED CHARGE DIFFUSION Subject matter disclosed herein relates to flash memory, and more particularly to a charge trap memory and a process flow to form same.... | 10/20/2011 |
| 20110255334 | FLASH MEMORY HAVING MULTI-LEVEL ARCHITECTURE Subject matter disclosed herein relates to a multi-level flash memory and a process flow to form same.... | 10/20/2011 |
| 20110216585 | METAL CONTAINING MATERIALS Metal containing materials and methods of forming the same are disclosed. One such method includes substantially concurrently feeding a flow of precursor gas containing a metal of a metal containing material and a flow of source gas containing a reducing agent so that t... | 09/08/2011 |
| 20110199819 | APPARATUS AND METHOD FOR EXTENDED NITRIDE LAYER IN A FLASH MEMORY A method and apparatus for storing information is provided. A core region of memory includes a semiconductor layer, at least one shallow trench, an insulator, and a charge-trapping layer. The semiconductor layer includes at least one source/drain region, and the insulat... | 08/18/2011 |
| 20110035637 | SYSTEMS AND DEVICES INCLUDING MEMORY WITH BUILT-IN SELF TEST AND METHODS OF MAKING AND USING THE SAME Disclosed are methods, systems and devices, such as a device including a data location, a quantizing circuit coupled to the data location, and a test module coupled to the quantizing circuit. The quantizing circuit may include an analog-to-digital converter, a switch co... | 02/10/2011 |
| 20110013449 | SELF-ALIGNED PATTERNING METHOD BY USING NON-CONFORMAL FILM AND ETCH BACK FOR FLASH MEMORY AND OTHER SEMICONDUCTUR APPLICATIONS A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal oxide is deposited over the charge trapping layer to form a thick oxide on top of the core source/drain region ... | 01/20/2011 |
| 20100246280 | SEMICONDUCTOR DEVICE HAVING RESET COMMAND A semiconductor device includes a reset sequence circuit, a latch circuit, and a reset control circuit. The reset sequence circuit is activated by receiving an externally input signal when a reset operation is started and outputs a first trigger signal. The latch circui... | 09/30/2010 |
| 20100157668 | Memory device and method of operating and fabricating the same A memory transistor including a substrate, a tunnel insulating pattern on the substrate, a charge storage pattern on the tunnel insulating pattern, a blocking insulating pattern on the charge storage pattern, and a gate electrode on the blocking insulating pattern, the ... | 06/24/2010 |
| 20100155804 | Shallow Trench Isolation For A Memory In some embodiments, a gate structure with a spacer on its side may be used as a mask to form self-aligned trenches in a microelectronic memory, such as a flash memory. A first portion of the gate structure may be used to form the mask, together with sidewall spacers, i... | 06/24/2010 |
| 20100142266 | VERTICAL FIELD-EFFECT TRANSISTOR A method produces a vertical field-effect transistor having a semiconductor layer, in which a doped channel region is arranged along a depression. A “buried” terminal region leads as far as a surface of the semiconductor layer. The field-effect transistor also has a... | 06/10/2010 |
| 20100097854 | FLASH MEMORY AND FLASH MEMORY ARRAY A flash memory including a substrate having a recess, a buried bit line, a word line, a single side insulating layer, a floating gate, a tunneling dielectric layer, a control gate, and an inter-gate dielectric layer is provided. The buried bit line extends below the rec... | 04/22/2010 |
| 20100070799 | DYNAMIC CELL BIT RESOLUTION A system and method, including computer software, is used to write to a flash memory device that includes multiple memory cells. One or more of the memory cells are written at a first resolution corresponding to a first number of bits of data. A signal to write at a sec... | 03/18/2010 |
| 20100027343 | Non-Volatile Memory Monitor The invention provides circuits, systems, and methods for monitoring a non-volatile memory (NVM) cell, or an array of NVM cells. The monitor is capable of switching from a normal operating state to an evaluation state, monitoring for one or more particular characteristi... | 02/04/2010 |
| 20100008141 | Strap-Contact Scheme for Compact Array of Memory Cells A semiconductor device with multiple strap-contact configurations for a memory cell array. An array with memory cells interconnected with bit-lines, control-gate lines, erase gate lines, common-source lines, and word-lines is provided. In one aspect of an illustrative e... | 01/14/2010 |
| 20090279355 | LOW POWER FLOATING BODY MEMORY CELL BASED ON LOW BANDGAP MATERIAL QUANTUM WELL Embodiments of the invention relate to apparatus, system and method for use of a memory cell having improved power consumption characteristics, using a low-bandgap material quantum well structure together with a floating body cell.... | 11/12/2009 |
| 20090251960 | HIGH TEMPERATURE MEMORY DEVICE Disclosed herein are various nonvolatile integrated device embodiments suitable for use at high temperatures. In some embodiments, a high temperature nonvolatile integrated device comprises a sapphire or spinel substrate having multiple ferroelectric memory cells dispos... | 10/08/2009 |
| 20090237990 | SONOS DEVICE WITH INSULATING STORAGE LAYER AND P-N JUNCTION ISOLATION The present invention provides a semiconductor device and a method for manufacturing thereof. The semiconductor device includes bit lines disposed in a semiconductor substrate, a first ONO disposed between the bit lines on the semiconductor substrate, and a second ONO f... | 09/24/2009 |
| 20090196106 | MEM SUSPENDED GATE NON-VOLATILE MEMORY A carrier storage node such as a floating gate is formed on a moving electrode with a control gate to form a suspended gate non-volatile memory, reducing floating gate to floating gate coupling and leakage current, and increasing data retention.... | 08/06/2009 |
| 20090168518 | CHIP SELECT CONTROLLER AND NON-VOLATILE MEMORY DEVICE INCLUDING THE SAME A chip select controller for a non-volatile memory device includes a first chip enable signal transfer unit, a second chip enable signal transfer unit, a first chip select pad, a second chip select pad, a third chip select pad and a chip select unit. The first chip enab... | 07/02/2009 |
| 20090150595 | BALANCED PROGRAMMING RATE FOR MEMORY CELLS A balanced program rate on NVM cells is achieved by (i) scrambling data bits and user bits; and (ii) shifting ED bits (of data and user bits) according to an incremental shift number, which may be the PBE-counter (which provides an incremental number). ED bits for the L... | 06/11/2009 |
| 20090140317 | Multiple Layer floating gate non-volatile memory device The disclosed systems and methods relate to floating gate non-volatile memory cells, with a floating gate comprising at least two layers constructed in different conductive or semiconductive materials. At least two of the layers of the floating gate are separated by an ... | 06/04/2009 |
| 20090134447 | Flash Memory Device and Method for Manufacturing the Same A flash memory device, and a manufacturing method thereof, having advantages of protecting sidewalls of a floating gate and a control gate and preventing a recess of an active area of a source region are provided. The method includes forming a tunneling oxide layer on a... | 05/28/2009 |
| 20090127613 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME A nonvolatile semiconductor memory device comprises a memory cell array of plural memory cells arranged in matrix. Each memory cell includes a first gate insulator layer formed on a semiconductor substrate, a floating gate formed on the semiconductor substrate with the ... | 05/21/2009 |
| 20090101960 | SEMICONDUCTOR MEMORY DEVICE According to an aspect of the present invention, there is provided a semiconductor memory device including: a semiconductor substrate having: a contact region; a select gate region; and a memory cell region; a first element isolation region formed in the contact region ... | 04/23/2009 |
| 20090097310 | MEMORY CELL STORAGE NODE LENGTH Methods, devices, and systems for a memory cell are provided. One embodiment includes a memory cell with a storage node separated from a body region by a first dielectric, wherein the body region includes a channel separating a source and a drain region, and wherein a l... | 04/16/2009 |
| 20090052238 | SEMICONDUCTOR INTEGRATED CIRCUIT A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, w... | 02/26/2009 |
| 20080316810 | MEMORY UNIT A memory unit is provided herein. Two non-volatile devices are used to store a logic state of the memory unit into the non-volatile devices. Although a power supply for the memory unit is shut down, the non-volatile devices still keep the data stored therein. The presen... | 12/25/2008 |
| 20080259682 | SEMICONDUCTOR DEVICE A semiconductor device includes a circuit forming area and a memory area including memory cells, first and second wells, a first conductor film formed over both wells and a second conductor film formed over the first well. First semiconductor regions are formed in the f... | 10/23/2008 |
| 20080259687 | Integrated Circuits and Methods of Manufacturing Thereof Embodiments of the invention relate to integrated circuits having a memory cell arrangement and methods of manufacturing thereof. In one embodiment of the invention, an integrated circuit has a memory cell arrangement which includes a fin structure extending in its long... | 10/23/2008 |
| 20080225593 | Single poly EEPROM without separate control gate nor erase regions A single-poly EEPROM memory device comprises source and drain regions in a semiconductor body, a floating gate overlying a portion of the source and drain regions, which defines a source-to-floating gate capacitance and a drain-to-floating gate capacitance, wherein the ... | 09/18/2008 |
| 20080225144 | Multi-purpose image sensor circuits, imager, system and method of operation Methods, devices, and systems for image sensors are disclosed that include a multi-mode circuit that can be configured for operating as an imaging pixel and a memory. The multi-mode circuit includes a photo-detector for collecting electrons generated by radiation imping... | 09/18/2008 |
| 20080205150 | HYBRID NON-VOLATILE MEMORY A non-volatile memory (NVM) circuit includes at least two types of NVM sub-circuits that share common support circuitry. Different types of NVM sub-circuits include ordinary NVM circuits that provide a logic output upon being addressed, programmable fuses that provide a... | 08/28/2008 |
| 20080205133 | Capacitor-less volatile memory cell, device, system and method of making same A capacitor-less memory cell, memory device, system and process of forming the capacitor-less memory cell includes forming the memory cell in an active area of a substantially physically isolated portion of the bulk semiconductor substrate. A pass transistor is formed o... | 08/28/2008 |
| 20080205147 | Local self-boost inhibit scheme with shielded word line A NAND architecture non-volatile memory device and programming process is described that reduces the effects of word line to word line voltage coupling by utilizing sets of two or more adjacent word lines and applying the same voltage to each in array access operations.... | 08/28/2008 |
| 20080170439 | Multi-level memory A storage system comprises a charge storage cell and a controller. The charge storage cell includes first and second charge storage regions, each capable of assuming a plurality of charge levels. The controller programs the first charge storage region to one of the plur... | 07/17/2008 |
| 20080158946 | ALTERNATING READ MODE Shifts in the apparent charge stored on a floating gate (or other charge storage element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other charge storing elements). To ac... | 07/03/2008 |
| 20080149989 | FLASH MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME Flash memory devices and methods for fabricating the same are provided. In accordance with an exemplary embodiment of the invention, a method for fabricating a memory device comprises the steps of fabricating a first gate stack and a second gate stack overlying a substr... | 06/26/2008 |
| 20080130359 | Multiple use memory chip A die for a memory array may store Flash and EEPROM bits in at least one Nitride Read Only Memory (NROM) array. Each array may store Flash, EEPROM or both types of bits.... | 06/05/2008 |
| 20080123421 | Memory architecture for separation of code and data in a memory device Code, data, and/or other information types, may be isolated from one another and stored in distinct regions within the memory array of a nonvolatile memory. The distinct regions in memory may have corresponding read/write interfaces that are optimized for each informati... | 05/29/2008 |
