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A method of swing on a swing is disclosed, in which a user positioned on a standard swing suspended by two chains from a substantially horizontal tree branch induces side to side motion by pulling alternately on one chain and then the other.
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| Application No. | Application Title | Issue Date |
| 20120081943 | Polarization-Coupled Ferroelectric Unipolar Junction Memory And Energy Storage Device A memory device is provided. The memory device includes a plurality of memory cells and a controller to write data to and read data from the memory cells. Each memory cell includes a first semiconductor material having a spontaneous polarization, a resistive ferroelectr... | 04/05/2012 |
| 20120020138 | TRANSISTOR HAVING AN ADJUSTABLE GATE RESISTANCE AND SEMICONDUCTOR DEVICE COMPRISING THE SAME A memory device comprises an array of memory cells each capable of storing multiple bits of data. The memory cells are arranged in memory strings that are connected to a common source line. Each memory cell includes a programmable transistor connected in series with a r... | 01/26/2012 |
| 20120009976 | RECESS GATE TRANSISTOR A method of forming a semiconductor device is provided, comprising forming a plurality of hard masks on a substrate by patterning an insulating layer; forming a plurality of trenches in the substrate, each trench having trench walls disposed between two adjacent masks a... | 01/12/2012 |
| 20110280075 | MEMORY DEVICE AND OPERATING METHOD THEREOF The invention provides a memory device on a substrate. The memory device comprises semiconductor layers, common word lines, common bit lines and a common source line. The semiconductor layers are stacked on the substrate, wherein each semiconductor layer has a plurality... | 11/17/2011 |
| 20110222336 | SEMICONDUCTOR DEVICE The invention provides a semiconductor device where data can be written after the production and forgery caused by rewriting of data can be prevented, and which can be manufactured at a low cost using a simple structure and an inexpensive material. Further, the inventio... | 09/15/2011 |
| 20110170343 | DRAM MEMORY CELL HAVING A VERTICAL BIPOLAR INJECTOR The invention relates to a memory cell having an FET transistor with a source, a drain and a floating body between the source and the drain, and an injector that can be controlled to inject a charge into the floating body of the FET transistor. The injector includes a b... | 07/14/2011 |
| 20110051525 | POWER SAVING METHOD AND CIRCUIT THEREOF FOR A SEMICONDUCTOR MEMORY A power saving method for a semiconductor memory is provided. The power saving method for a semiconductor memory including the steps of receiving a plurality of address codes, each of which has a first part code and a second part code; and activating a first boost proce... | 03/03/2011 |
| 20110032743 | Colloidal-Processed Silicon Particle Device Colloidal-processed Si particle devices, device fabrication, and device uses have been presented. The generic device includes a substrate, a first electrode overlying the substrate, a second electrode overlying the substrate, laterally adjacent the first electrode, and ... | 02/10/2011 |
| 20110007544 | Non-Volatile Memory with Active Ionic Interface Region A non-volatile memory cell and method of use therefore are disclosed. In accordance with various embodiments, the memory cell comprises a tunneling region disposed between a conducting region and a metal region, wherein the tunneling region comprises an active interface... | 01/13/2011 |
| 20100315871 | DYNAMIC DATA RESTORE IN THYRISTOR-BASED MEMORY DEVICE A dynamically-operating restoration circuit is used to apply a voltage or current restore pulse signal to thyristor-based memory cells and therein restore data in the cell using the internal positive feedback loop of the thyristor. In one example implementation, the int... | 12/16/2010 |
| 20100302854 | Area-Efficient Electrically Erasable Programmable Memory Cell Electrically erasable programmable “read-only” memory (EEPROM) cells in an integrated circuit, and formed by a single polysilicon level. The EEPROM cell consists of a coupling capacitor and a combined read transistor and tunneling capacitor. The capacitance of the c... | 12/02/2010 |
| 20100302848 | TRANSISTOR HAVING PERIPHERAL CHANNEL Transistors for use in semiconductor integrated circuit devices including a first source/drain region of the transistor is formed around a perimeter of a channel region, and a second source/drain region formed to extend below the channel region such that the channel reg... | 12/02/2010 |
| 20100290271 | ONE-TRANSISTOR, ONE-RESISTOR, ONE-CAPACITOR PHASE CHANGE MEMORY Memory devices and methods for operating such devices are described herein. A memory cell as described herein comprises a transistor electrically coupled to first and second access lines. A programmable resistance memory element is arranged along a current path between ... | 11/18/2010 |
| 20100284218 | SUPERLATTICE DEVICE, MANUFACTURING METHOD THEREOF, SOLID-STATE MEMORY INCLUDING SUPERLATTICE DEVICE, DATA PROCESSING SYSTEM, AND DATA PROCESSING DEVICE To include a superlattice laminate having laminated thereon a first crystal layer of which crystal lattice is a cubic crystal and in which positions of constituent atoms are reversibly replaced by application of energy, and a second crystal layer having a composition di... | 11/11/2010 |
| 20100254185 | NONVOLATILE MEMORY APPARATUS AND METHOD OF USING THIN FILM TRANSISTOR AS NONVOLATILE MEMORY The present invention relates to a nonvolatile memory apparatus and a method of using a thin film transistor (TFT) as a nonvolatile memory by storing carriers in a body of the TFT, which operates a general TFT as a memory cell of a nonvolatile memory by manipulating the... | 10/07/2010 |
| 20100246252 | NONVOLATILE SOLID STATE MAGNETIC MEMORY AND RECORDING METHOD THEREOF A nonvolatile solid state magnetic memory with a ultra-low power consumption and a recording method thereof, the memory including a magnetic material having a magnetic anisotropy that can be changed by increasing or decreasing a carrier concentration, wherein a directio... | 09/30/2010 |
| 20100238716 | SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR DEVICE GROUP A semiconductor device includes a first CMOS inverter, a second CMOS inverter, a first transfer transistor and a second transfer transistor wherein the first and second transfer transistors are formed respectively in first and second device regions defined on a semicond... | 09/23/2010 |
| 20100214823 | SEMICONDUCTOR DEVICE INCLUDING MEMORY CELL HAVING CAPACITOR A semiconductor device includes a semiconductor substrate; a memory cell array including a plurality of memory cells formed on the semiconductor substrate and arranged in a matrix in a first direction and a second direction on the surface of the semiconductor substrate;... | 08/26/2010 |
| 20100202187 | DATA READ/ WRITE DEVICE A data read/write device according to an example of the present invention includes a recording layer, and means for applying a voltage to the recording layer, generating a resistance change in the recording layer, and recording data. The recording layer is composed of a... | 08/12/2010 |
| 20100195392 | CAPACITOR STRUCTURE HAVING IMPROVED AREA EFFICIENCY, A MEMORY DEVICE INCLUDING THE SAME, AND A METHOD OF FORMING THE SAME Semiconductor structures including a plurality of conductive structures having a dielectric material therebetween are disclosed. The thickness of the dielectric material spacing apart the conductive structures may be adjusted to provide optimization of capacitance and v... | 08/05/2010 |
| 20100176481 | Memory Device and Manufacturing Method Thereof A memory device and a manufacturing method thereof are provided. The manufacturing method of memory device includes the following steps. Firstly, a substrate having a substrate surface is provided. Next, at least two memory units separated via a space are formed on the ... | 07/15/2010 |
| 20100177553 | REWRITABLE MEMORY DEVICE Memory devices described herein are programmed and erased by physical segregation of an electrically insulating layer out of a memory material to establish a high resistance state, and by re-absorption of at least a portion of the electrically insulating layer into the ... | 07/15/2010 |
| 20100157667 | Capacitorless DRAM memory cell comprising a partially-depleted MOSFET device comprising a gate insulator in two parts The capacitorless DRAM memory cell is constituted by a partially-depleted MOSFET device successively comprising a base substrate, a buried insulator, a floating substrate from semiconducting material including a channel, the gate insulator and a gate. The gate comprises... | 06/24/2010 |
| 20100149864 | MEMORY CIRCUIT WITH QUANTUM WELL-TYPE CARRIER STORAGE Data is stored in a quantum-well type structure with double gate control. According to an example embodiment, a transistor-based data storage circuit includes a gate, a back gate and a semiconductor channel between the gate and the back gate. Carriers are stored in a st... | 06/17/2010 |
| 20100149854 | SEMICONDUCTOR DEVICE STORAGE CELL STRUCTURE, METHOD OF OPERATION, AND METHOD OF MANUFACTURE A method of fabricating an integrated circuit device storage cell may include forming a channel region comprising a semiconductor material doped to a first conductivity type; forming a store gate structure comprising a semiconductor material doped to a second conductivi... | 06/17/2010 |
| 20100135073 | ORGANIC ELECTRONIC MEMORY COMPONENT, MEMORY COMPONENT ARRANGEMENT AND METHOD FOR OPERATING AN ORGANIC ELECTRONIC MEMORY COMPONENT The invention relates to an organic electronic memory component having an electrode and a counterelectrode and an organic layer arrangement formed between said electrode and counterelectrode and in electrical contact herewith. wherein the organic layer arrangement compr... | 06/03/2010 |
| 20100135071 | MICROELECTRONIC PROGRAMMABLE DEVICE AND METHODS OF FORMING AND PROGRAMMING THE SAME A microelectronic programmable structure and methods of forming and programming the structure are disclosed. The programmable structure generally includes an ion conductor and a plurality of electrodes. Electrical properties of the structure may be altered by applying a... | 06/03/2010 |
| 20100128533 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME A nonvolatile memory device includes a plurality of strings each of which is configured with a first select transistor, a second select transistor, and a plurality of memory cells connected in series between the first and second select transistors. A common source line ... | 05/27/2010 |
| 20100118579 | Nand Based Resistive Sense Memory Cell Architecture Various embodiments are directed to an apparatus comprising a semiconductor memory array with non-volatile memory unit cells arranged into a NAND block. Each of the unit cells comprises a resistive sense element connected in parallel with a switching element. The resist... | 05/13/2010 |
| 20100110765 | Non-Volatile Memory Cell with Programmable Unipolar Switching Element A non-volatile memory cell with a programmable unipolar switching element, and a method of programming the memory element are disclosed. In some embodiments, the memory cell comprises a programmable bipolar resistive sense memory element connected in series with a progr... | 05/06/2010 |
| 20100110759 | PROGRAMMABLE RESISTIVE MEMORY CELL WITH FILAMENT PLACEMENT STRUCTURE Programmable metallization memory cells having a first metal contact and a second metal contact with an ion conductor solid electrolyte material between the metal contacts. The first metal contact has a filament placement structure thereon extending into the ion conduct... | 05/06/2010 |
| 20100110753 | Ferroelectric Memory Cell Arrays and Method of Operating the Same An integrated circuit includes a plurality of switching devices, wherein each device includes a gate dielectric capable of assuming at least a first and a second polarization state. The integrated circuit further includes an address circuit configured to control bit lin... | 05/06/2010 |
| 20100097853 | Jeet memory cell A memory cell (FIG. 6A) compatible with dynamic random access memories (DRAM) and static random access memories (SRAM) is disclosed. The memory cell includes a first junction field effect transistor (600) having a first conductivity type. A second junction... | 04/22/2010 |
| 20100091543 | SEMICONDUCTOR MEMORY APPARATUS INCLUDING A COUPLING CONTROL SECTION A semiconductor memory apparatus is disclosed having a dual open bit line structure In the dual open bit line structure, bit lines or bit line bars are each arranged side by side in adjoining cell mats. The semiconductor memory apparatus includes a coupling control sect... | 04/15/2010 |
| 20100080055 | SEMICONDUCTOR MEMORY DEVICE Disclosed herein is a semiconductor memory device which prevents the voltage of a select bit line from being reduced due to the action of coupling capacitance between the select bit line and a non-select bit line, reduces current consumption, and enables high speed read... | 04/01/2010 |
| 20100067294 | SEMICONDUCTOR MEMORY DEVICE A semiconductor memory device includes: an input pad set configured to receive an external input signal and a reference voltage; an input buffer set configured to detect and transmit the input signal to an internal circuit of the semiconductor memory device by comparing... | 03/18/2010 |
| 20100052729 | DIGITAL DATA INVERSION FLAG GENERATOR CIRCUIT An integrated circuit includes an array of memory cells and a digital flag generator circuit configured to generate a data inversion flag based on whether a number of logical zero bits contained in a data word to be transmitted from the memory cells is greater than a th... | 03/04/2010 |
| 20100054018 | SEMICONDUCTOR MEMORY DEVICE AND INFORMATION PROCESSING SYSTEM A semiconductor memory device comprises a memory cell array and a forming controller. The memory cell array includes a plurality of first memory cells each having a structure in which dielectric material is sandwiched between two electrodes, and the memory cell array is... | 03/04/2010 |
| 20100046304 | NON-VOLATILE MEMORY DEVICE AND ERASE METHOD Provided is a non-volatile memory device including first and second, vertically stacked semiconductor substrates, a plurality of non-volatile memory cell transistors formed in a row on the first and second semiconductor substrates, and a plurality of word lines connecte... | 02/25/2010 |
| 20100046269 | Programmable read only memory An array of memory cells is disclosed. The memory cell includes a fuse and at least one transistor. The transistor is used to control the programming or sensing of the fuse. A program voltage is applied to a stack of first and second conductive layers. A first portion o... | 02/25/2010 |
