Bizarre Patents
Method and apparatus for making a drink hop along a bar or counter
A method for generating a drink which appears to hop from a remote spot on the bar or counter and take one or more leaps, before landing in a patron's glass.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Application No. | Application Title | Issue Date |
| 20110211090 | REGISTER CONFIGURATION CONTROL DEVICE, REGISTER CONFIGURATION CONTROL METHOD, AND PROGRAM FOR IMPLEMENTING THE METHOD A resister configuration control device which is capable of updating resister configuration values during a non-display period without increasing a circuit scale. A FIFO selector 103 receives register configuration value information comprising a register configur... | 09/01/2011 |
| 20110074795 | GRAPHIC DATA PROCESSING MODULE AND DATA LINE DRIVING CIRCUIT USING THE SAME A graphic data processing module includes a system interface for receiving image data streams, a shift register connected to the system interface, a timing generator connected to the system interface and the shift register, and a graphic display data random access memor... | 03/31/2011 |
| 20110032264 | CORRECTION CIRCUIT AND DISPLAY DEVICE A correction circuit includes a memory that stores a mobility correction value or a threshold voltage correction value for correcting luminance non-uniformity for every pixel, a memory read-out unit that reads out the mobility correction value or the threshold voltage c... | 02/10/2011 |
| 20110007085 | MEMORY CALIBRATION METHOD AND DISPLAY APPARATUS APPLYING THE SAME A memory calibration method and a display apparatus using the memory calibration method are provided. The memory calibration method includes displaying an automatic calibration item, determining whether an automatic calibration command is input through the automatic cal... | 01/13/2011 |
| 20100328334 | Register Allocation for Message Sends in Graphics Processing Pipelines Message sends may be implemented in a graphics pipeline using biased graph coloring. Registers may be allocated by shaders for message sends using biased graph coloring.... | 12/30/2010 |
| 20100302266 | INTEGRATED CIRCUIT APPARATUS, ELECTRO-OPTICAL APPARATUS, AND ELECTRONIC EQUIPMENT An integrated circuit apparatus includes data-line drive circuits, an offset register that stores offset set values corresponding to a plurality of pixels, and correction circuits that perform processing of correcting the offsets on the basis of the offset set values. T... | 12/02/2010 |
| 20100123728 | MEMORY ACCESS CONTROL CIRCUIT AND IMAGE PROCESSING SYSTEM A memory access control circuit includes a first internal register, an address transmitting unit that sets a state of the first internal register to a first state to transmit a first address and sets a state of the first internal register to a second state to transmit a... | 05/20/2010 |
| 20100103185 | SWITCH PIN MULTIPLEXING An integrated circuit (IC) within an IC package, where the IC includes a memory control module and a timing module. The memory control module is configured to control read/write operations of a memory IC via N pins of the IC package, where N is an integer greater than 1... | 04/29/2010 |
| 20100103184 | Driving Circuit for Detecting Line Short defects For detecting line short defects in a display panel, a driving circuit has a plurality of shift registers, a plurality of diode modules, and at least one power supply. Each shift register has an output port for outputting a driving signal sequentially. The diode modules... | 04/29/2010 |
| 20100079475 | DISPLAYPORT CONTROL AND DATA REGISTERS Circuits, methods, and apparatus for registers to store information that may be used by devices in a display system. One example provides control and data registers in a display to store information pertaining to a display system that includes the display. The registers... | 04/01/2010 |
| 20090115792 | BIDIRECTIONAL SHIFT REGISTER AND DISPLAY DEVICE USING THE SAME A device, in which circuit size is small and operation is stable, comprises a plurality of serially connected unit registers (shift registers) in which transfer is controlled by any of three or more clock signals each having a different phase, and a setting signal which... | 05/07/2009 |
| 20090085919 | SYSTEM AND METHOD OF MAPPING SHADER VARIABLES INTO PHYSICAL REGISTERS The present disclosure includes system and method of mapping shader variables into physical registers. In an embodiment, a graphics processing unit (GPU) and a memory coupled to the GPU are disclosed. The memory includes a processor readable data file that has a registe... | 04/02/2009 |
| 20090073147 | Driving IC for display apparatus, display apparatus and setting data programming method thereof A driving integrated circuit (IC) in which operations of registers and a method of programming setting data are improved, a display apparatus including the same, and the method of programming setting data of the display apparatus are provided. The display apparatus incl... | 03/19/2009 |
| 20090033672 | SCHEME FOR VARYING PACKING AND LINKING IN GRAPHICS SYSTEMS A wireless device which performs a first-level compiler packing process and a second-level hardware packing process on varyings. The compiler packing process packs two or more shader variables (varyings or attributes) whose sum of components equals M into a shared M-dim... | 02/05/2009 |
| 20080303846 | Assymetric two-pass graphics scaling A method and an apparatus for determining an up scale factor and a down scale factor according to a scale factor received from a graphics application program interface (API) to scale a graphics data in a graphics processing unit (GPU) are described. The up scale factor ... | 12/11/2008 |
| 20080284789 | Image processing circuit an image processing circuit includes a memory storing an image data, which includes a plurality of line data disposed regularly a first module performing a plurality of thinning processes, at each of which a plurality of line data are readout from the memory, and at eac... | 11/20/2008 |
| 20080278513 | Plotting Apparatus, Plotting Method, Information Processing Apparatus, and Information Processing Method Registers 32a-32d hold data for pixels interleaved. An operator 34 reads the pixel data from the registers and processes the pixel data in accordance with a program code. The operator 34 writes the result of the process back to ... | 11/13/2008 |
| 20080170082 | GRAPHICS ENGINE AND METHOD OF DISTRIBUTING PIXEL DATA A graphics engine and related method of operation are disclosed in which a pixel distributor distributes pixel data across a plurality of pixel shaders using a first approach when the presence of one or more rendering features is indicated, else using a second approach ... | 07/17/2008 |
| 20080165201 | FLAT DISPLAY DEVICE AND SIGNAL DRIVING METHOD OF THE SAME A flat display device has a circuit configuration in which a division-driving system and an aspect conversion are integrated with each other, and performs driving appropriate to achieve higher resolution even in driving a display unit. The device comprises a memory circ... | 07/10/2008 |
| 20080158238 | FORMAT CONVERSION APPARATUS FROM BAND INTERLEAVE FORMAT TO BAND SEPARATE FORMAT A format conversion apparatus which converts image data of a band interleave format into image data of a band separate format is provided. The apparatus includes a memory which stores image data of a band interleave format; and a converting module which reads the memory... | 07/03/2008 |
| 20070296729 | Unified virtual addressed register file A multi-threaded processor is provided, such as a shader processor, having an internal unified memory space that is shared by a plurality of threads and is dynamically assigned to threads as needed. A mapping table that maps virtual registers to available internal addre... | 12/27/2007 |
| 20070195103 | Memory region access management A memory region access management technique. More particularly, at least one embodiment of the invention relates to a technique to partition memory between two or more operating systems or other software running on one or more processors. ... | 08/23/2007 |
| 20070126748 | Hardware animation of a bouncing image A graphics controller for animating an overlay is described. The graphics controller includes a host interface for communicating with an external processor and a plurality of registers in communication with the host interface. Logic is configured to periodically change ... | 06/07/2007 |
| 20070070075 | Register-collecting mechanism, method for performing the same and pixel processing system employing the same A pixel processing system includes a register-collecting mechanism and a pixel shader. The register-collecting mechanism corrects a first program to a second program. The first program requires a number of first registers. The second program requires a portion of the fi... | 03/29/2007 |
| 20060250404 | System and method for programming a controller A system for configuring a chip to perform certain operations is provided. The system includes a CPU. The CPU is in communication with a graphics controller. The graphics controller includes a non-volatile memory for storing a look up table (LUT). The graphics controlle... | 11/09/2006 |
| 20060066630 | Apparatus and method for transmitting data between graphics controller and external storage A graphics controller and associated method of operation is provided. The graphics controller includes a memory for receiving image data from an image producing source. The graphics controller also includes an image data wrapper module having circuitry that operates ind... | 03/30/2006 |
| 20060061582 | Apparatus and method for edge handling in image processing A method and apparatus for hardware-base edge handling in video post-processing. In one embodiment, the method includes the identification of at least one unstored input pixel required to compute an output pixel during output pixel computation. Once identified, a pixel ... | 03/23/2006 |
| 20060001672 | Searchable registers The invention relates to a device for displaying information, data and/or input elements on an interface (4), in particular on a screen, with at least one register (1) for displaying a subset of information, data and/or input elements, with the at least on... | 01/05/2006 |
| 20050280654 | API communications for vertex and pixel shaders A three-dimensional API for communicating with hardware implementations of vertex shaders and pixel shaders having local registers. With respect to vertex shaders, API communications are provided that may make use of an on-chip register index and API communications are ... | 12/22/2005 |
| 20050259105 | System and method for detecting memory location modifications to initiate image data transfers A system and method for detecting memory location modifications to initiate image data transfers includes a display controller device with a location detector module and controller logic. The location detector module detects register write operations from a host central... | 11/24/2005 |
| 20050237333 | Graphics drawing apparatus and method of same A graphics drawing apparatus able to reduce the amount of data transferred, able to realize a lower power consumption, and consequently able to achieve an improvement of performance of the system as a whole, provided with address generator for automatically generating a... | 10/27/2005 |
| 20050128207 | API communications for vertex and pixel shaders A three-dimensional API for communicating with hardware implementations of vertex shaders and pixel shaders having local registers. With respect to vertex shaders, API communications are provided that may make use of an on-chip register index and API communications are ... | 06/16/2005 |
