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| Application No. | Application Title | Issue Date |
| 20120038497 | Transmission Interface and System Using the Same A transmission interface includes a first pin, a second pin, a conversion unit, and a decoding unit. The conversion unit receives a serial input data stream via the first pin and receives a serial clock via the second pin. The conversion unit converts the serial input d... | 02/16/2012 |
| 20110181556 | SERIAL-PARALLEL-CONVERSION CIRCUIT, DISPLAY EMPLOYING IT, AND ITS DRIVE CIRCUIT The present invention relates to a serial-parallel conversion circuit of a display device. First latch circuits for sampling and latching a serial signal in accordance with sampling pulses outputted from a shift register (31) are pro... | 07/28/2011 |
| 20110156937 | Multi-Speed Burst Mode Serializer/De-Serializer A multi-speed burst mode serializer/de-serializer (SerDes) is configurable and can operate in one of a plurality of operating modes. The plurality of operating modes correspond to the reception of signals from optical network units that operate at different nominal spee... | 06/30/2011 |
| 20110156936 | MOBILE INDUSTRY PROCESSOR INTERFACE An optimized Mobile Industry Processor Interface (MIPI) includes a transmitter physical (PHY) layer configured to convert input data into serial data and transmit the serial data in synchronization with a high-speed clock, a receiver PHY layer configured to convert the ... | 06/30/2011 |
| 20110109486 | PSEUDO-ORTHOGONAL CODE GENERATOR A pseudo-orthogonal code generator is provided. The pseudo-orthogonal code generator simplifies overall configuration and provides a more efficient operating speed by implementing a pseudo-orthogonal code generator using combined circuits instead of using a read only me... | 05/12/2011 |
| 20110090099 | System and method for encoding and decoding serial signals formed by a plurality of color lights The present invention is to provide a method for encoding and decoding serial signals formed by a plurality of color lights, which is applied to an encoding/decoding system comprising an encoding device and a decoding device, and comprises steps of generating a driving ... | 04/21/2011 |
| 20110090100 | TRANSFORMING SIGNALS USING PASSIVE CIRCUITS Passive signal combiners are employed to transform at least one signal from one domain to another. In some aspects the transformation comprises an NFL an IFFT, a DFT, or an IDFT. In some implementations the passive signal combiners comprise a set of planar waveguides (e... | 04/21/2011 |
| 20110057819 | Semiconductor device having plural semiconductor chips laminated to each other In a stacked semiconductor device in which a plurality of through silicon vias used for data transfer are shared among a plurality of semiconductor chips, a first semiconductor chip included in the semiconductor chips holds through silicon via switching information for ... | 03/10/2011 |
| 20110018747 | Data Generator Providing Large Amounts of Data of Arbitrary Word Length A waveform memory 66 stores data streams with each data stream having M-bit parallel data. A sequence memory 60 stores sequence information and data discard information on the amount of data to discard from the last data in each data stream. A sequencer 01/27/2011 | |
| 20110012761 | SEMICONDUCTOR INTEGRATED DEVICE In one embodiment, a semiconductor integrated device includes a plurality of semiconductor chips each having a first internal circuit and a second internal circuit and being stacked while displaced from each other. The first internal circuit processes a data signal in a... | 01/20/2011 |
| 20110006932 | PROGRAMMABLE DESERIALIZER A deserializer for converting serial data into at least one parallel data includes a first flip-flop group, a second flip-flop group and a programmable frequency divider. The first flip-flop group includes a plurality of flip-flops connected in series, where the first f... | 01/13/2011 |
| 20100328116 | DEVICES FOR CONVERSION BETWEEN SERIAL AND PARALLEL DATA Serial-to-parallel and parallel-to-serial conversion devices may provide for efficient conversion of serial bit streams into parallel data units (and vice versa). In one implementation, a device may include delay circuits, each of which being configured to receive a ser... | 12/30/2010 |
| 20100321573 | METHOD AND APPARATUS FOR CONNECTING HDMI DEVICES USING A SERIAL FORMAT An apparatus and a method for providing serialized HDMI data from an HDMI source to an HDMI sink. An HDMI transmitter may include inputs including control inputs, a deserializer, and a parser. The inputs may receive serialized HDMI data from an HDMI data source. A deser... | 12/23/2010 |
| 20100302079 | METHOD FOR ALIGNING A SERIAL BIT STREAM WITH A PARALLEL OUTPUT The invention relates to a method and circuit for aligning a serial bit stream with a parallel output. The method comprises latching Q bits from the serial bit stream into a register, locating a position P of a first bit of a start of frame delimiter (SFD) in the regist... | 12/02/2010 |
| 20100238983 | SYSTEM AND METHOD FOR DATA TRANSMISSION BETWEEN AN INTELLIGENT ELECTRONIC DEVICE AND A REMOTE DEVICE A system and method for data transmission between an intelligent electronic device (IED) and a device, such as a remote display or input/output (I/O) device, are provided. Each data line of the IED is input into a serializer and transmitted over a serial link to a deser... | 09/23/2010 |
| 20100238055 | SIGNAL TRANSMISSION SYSTEM AND SIGNAL CONVERSION CIRCUIT A signal transmission system in which a serializer IC connected to first parallel signal wirings and a deserializer IC connected to second parallel signal wirings are connected by a transmission line. Among input terminals of the serializer IC, redundant input terminals... | 09/23/2010 |
| 20100149137 | PARALELL-SERIAL CONVERSION CIRCUIT, AND ELECTRONIC DEVICE USING THE CIRCUIT A parallel-serial conversion circuit in which clock frequency and data width can be flexibly configured. The parallel-serial conversion circuit converts m×n bit parallel data (m and n being natural numbers), of clock frequency f, into 1-bit serial data of clock frequen... | 06/17/2010 |
| 20100128542 | Reference Clock and Command Word Alignment A memory system includes a memory controller that issues command signals and a reference-clock signal to a memory device. The edge rate of the reference-clock signal is lower than the bit rate of the command signals, so the memory device multiplies the reference clock s... | 05/27/2010 |
| 20100103002 | HIGH-SPEED SERIAL INTERFACE CIRCUIT AND ELECTRONIC INSTRUMENT A high-speed serial interface circuit includes a data receiver circuit, a clock signal receiver circuit, a logic circuit block that includes at least a serial/parallel conversion circuit, a free-running clock signal generation circuit, a clock signal detection circuit, ... | 04/29/2010 |
| 20100097249 | SERIAL SIGNAL RECEIVING DEVICE, SERIAL TRANSMISSION SYSTEM AND SERIAL TRANSMISSION METHOD A serial signal receiving device, includes: a serial-parallel converter that converts a transmitted serial signal into a parallel signal, wherein the serialized signal is obtained by the plural signal; a storage unit that stores phase difference information indicating a... | 04/22/2010 |
| 20100079316 | Digital signal transmitting apparatus and digital signal transmitting method A digital signal transmitting apparatus includes an encoder which converts parallel input signals of multiple channels into serial data in a manner synchronized with a first clock signal, and a decoder which converts the serial data into parallel output signals of the m... | 04/01/2010 |
| 20100045493 | SYSTEM AND METHOD FOR FLEXIBLE PHYSICAL LAYOUT IN A HETEROGENEOUS CONFIGURABLE INTEGRATED CIRCUIT A system including a serializer/deserializer (SERDES) block including a first SERDES lane, a second SERDES lane, a third SERDES lane, and a fourth SERDES lane; a physical coding sublayer (PCS) block including a layout select tag, a first PCS lane connected to the fourth... | 02/25/2010 |
| 20090261997 | Multi-Speed Burst Mode Serializer/De-Serializer A multi-speed burst mode serializer/de-serializer (SerDes) is configurable and can operate in one of a plurality of operating modes. The plurality of operating modes correspond to the reception of signals from optical network units that operate at different nominal spee... | 10/22/2009 |
| 20090243899 | Interface control circuit An interface control circuit including a physical layer receiver, a lane receiver, a bridge circuit, a transmitter command encoder, a lane transmitter and a physical layer transmitter is provided. The physical layer receiver receives and converts serial data into parall... | 10/01/2009 |
| 20090231171 | LOW POWER SERDES ARCHITECTURE USING SERIAL I/O BURST GATING A serializer/deserializer is disclosed with a flexible design that allows for sending data streams between computer systems where the power dissipation is markedly reduced by placing the serializer/deserializer in a standby, low power mode between the sending of data. W... | 09/17/2009 |
| 20090231172 | CIRCUIT AND METHOD FOR DRIVING, ELECTRO-OPTIC DEVICE, AND ELECTRONIC APPARATUS There is provided a driving circuit that drives an electro-optic device by outputting data signals that are subjected to serial-to-parallel conversion into m channels through m (m is a natural number greater than or equal to 2) image signal lines to a plurality of data ... | 09/17/2009 |
| 20090231170 | APPARATUS AND METHOD FOR DIGITAL FREQUENCY DOWN-CONVERSION Disclosed is an apparatus and a method for down-converting frequencies of an input signal by separating the signal to which at least two frequencies are allocated according to each frequency, and then outputting at least two digital IF signals in a communication system.... | 09/17/2009 |
| 20090224801 | PATTERN MATCHING APPARATUS A pattern matching apparatus for matching input data to a reference data string, wherein: it is implemented in electronic hardware and can be implemented using commercially available FPGAs using all digital processing; it is capable of very fast correlation; input data ... | 09/10/2009 |
| 20090207057 | Dual Purpose Serializer/De-Serializer for Point-To-Point and Point-To-Multipoint Communication A dual purpose serializer/de-serializer (SerDes) for point-to-point and point-to-multipoint communication. A configurable SerDes can be designed to operate in one of a plurality of operating modes. Selection between the plurality of operating modes can be based on infor... | 08/20/2009 |
| 20090167573 | Data transmission circuits and data transceiver systems A data transmission circuit is disclosed. The transmission circuit includes a serial clock generator, a serializer and a transmission clock generator. The serial clock generator generates a serial clock. The serializer serializes N-bit parallel data to N-bit serial data... | 07/02/2009 |
| 20090167572 | Serial/Parallel data conversion apparatus and method thereof A serial/parallel data conversion apparatus and a method thereof are used to convert serial data into parallel data by a delay pulse and three stage registers, wherein the device includes a first data register, a second data register, a third data register, a frequency ... | 07/02/2009 |
| 20090146852 | MULTI-SPEED BURST MODE SERIALIZER/DE-SERIALIZER A multi-speed burst mode serializer/de-serializer (SerDes). A configurable SerDes can be designed to operate in one of a plurality of operating modes. The plurality of operating modes correspond to the reception of signals from optical network units that operate at diff... | 06/11/2009 |
| 20090135032 | DUAL PURPOSE SERIALIZER/DE-SERIALIZER FOR POINT-TO-POINT AND POINT-TO-MULTIPOINT COMMUNICATION A dual purpose serializer/de-serializer (SerDes) for point-to-point and point-to-multipoint communication. A configurable SerDes can be designed to operate in one of a plurality of operating modes. Selection between the plurality of operating modes can be based on infor... | 05/28/2009 |
| 20090128380 | Current-controlled CMOS logic family Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR g... | 05/21/2009 |
| 20090109071 | SERIAL DATA ANALYSIS IMPROVEMENT A method for improving performance and flexibility of serial data analysis in test instruments, is independent of data bit rate, encoding scheme or communication protocol embodied in the serial data. The serial data is input to a transmitter section, where it is demulti... | 04/30/2009 |
| 20090096644 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, PATTERN DETECTION METHOD AND SERIAL-PARALLEL CONVERSION METHOD A shift register SR configured to successively take in and hold input serial data on the basis of a first clock signal, a pattern detection section configured to detect a predetermined pattern contained in the serial data taken in the shift resister and a second clock g... | 04/16/2009 |
| 20090091480 | HIGH-FREQUENCY MODULE FOR PERFORMING EFFECTIVE PHASE COMPENSATION OF CLOCK FOR INPUT DIGITAL SIGNAL A high-frequency module includes a high-speed logic circuit for processing an input digital signal having a transmission rate of several tens of Gbps by detecting the level of the input digital signal by using a clock having a frequency of several tens of GHz; a variabl... | 04/09/2009 |
| 20090073010 | DATA CONVERSION A circuit includes a data conversion circuit including a first input configured to receive a first serial data stream, a second input configured to receive a second serial data stream, and a third input configured to receive a third serial data stream. A first sampling ... | 03/19/2009 |
| 20090066546 | HIGH-SPEED SERIAL INTERFACE CIRCUIT AND ELECTRONIC INSTRUMENT A high-speed serial interface circuit includes a data receiver circuit, a clock signal receiver circuit, a logic circuit block that includes at least a serial/parallel conversion circuit, a free-running clock signal generation circuit, a clock signal detection circuit, ... | 03/12/2009 |
| 20090040082 | DEVICE FOR PROCESSING BINARY DATA WITH SERIAL/PARALLEL CONVERSION A device for processing binary data comprises at least one transmission link having an input for receiving a serial bit stream and an output for forwarding bits in a parallel format, and a serial/parallel converter providing n≧2 successive data bits of the serial bit ... | 02/12/2009 |
