Class 327/161 - With delay means

Subclass of Class 327 - Miscellaneous active electrical nonlinear devices, circuits, and systems
Definition: Subject matter including means providing a distinct signal
No. of applications: 212
Last issue date: 05/24/2012

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Application No.	Application Title	Issue Date
20120126869	TIMING SKEW ERROR CORRECTION APPARATUS AND METHODS Apparatus and methods disclosed herein operate to compensate for skew between inverse phases (e.g., differential phases) of an analog signal appearing at the inputs of an analog signal capture circuit such as a track-and-hold or sample-and-hold circuit associated with a...	05/24/2012
20120068748	Phase Detection Method and Phase Detector This invention relates to a phase detection method. An input signal (51, 91, 111) is sampled (13, 14, 15, 16) for obtaining several samples (1, 2, 3) at different points in time which are defined by a clock (C). A phase control signal (4, 5) ...	03/22/2012
20120044004	TRACK AND HOLD ARCHITECTURE WITH TUNABLE BANDWIDTH To date, bandwidth mismatch within time-interleaved (TI) analog-to-digital converters (ADCs) has been largely ignored because compensation for bandwidth mismatch is performed by digital post-processing, namely finite impulse response filters. However, the lag from digit...	02/23/2012
20120044776	SEMICONDUCTOR DEVICE AND CONTROL METHOD THEREOF A semiconductor device comprises: a control signal generating circuit that generates and outputs a control signal that is in an active state during a period around at least one of rising edges and falling edges of a clock signal; and a data input circuit that is control...	02/23/2012
20110316601	Method and Device for Delaying Activation Timing of Output Device A delay method for determining an activation moment of an output device in a circuit system is disclosed. The delay method includes determining resistance of an over-current flag pull-high resistor of the circuit system, generating a current according to the resistance ...	12/29/2011
20110316602	SYSTEMS AND METHODS OF INTEGRATED CIRCUIT CLOCKING Various systems and methods are provided for integrated circuit clocking. In one embodiment, an integrated circuit system includes a plurality of combinational logic groups, each combinational logic group having a propagation time; and means for delaying a synchronizing...	12/29/2011
20110316600	Serial Link Receiver and Method Thereof A method and apparatus of clock recovery is disclosed. The apparatus comprising: a first delay circuit for receiving an input data signal and outputting a delayed data signal; an edge extraction circuit for outputting an edge signal by detecting a transition in the inpu...	12/29/2011
20110304369	METHOD FOR SOURCE SYNCHRONOUS HIGH-SPEED SIGNAL SYNCHRONIZATION A source synchronous signal synchronization system includes a differential signal receiver; a tunable input delay element coupled to the receiver; an input serializer/deserializer (ISerDes) coupled to the tunable input delay; an alignment unit coupled to the ISerDes; an...	12/15/2011
20110298512	CIRCUIT, SYSTEM AND METHOD FOR CONTROLLING READ LATENCY A read latency control circuit is described having a clock synchronization circuit and a read latency control circuit. The clock synchronization circuit includes an adjustable delay line to generate an output clock signal whose phase is synchronized with the phase of th...	12/08/2011
20110298510	VOLTAGE-CONTROLLED DELAY LINES, DELAY-LOCKED LOOP CIRCUITS INCLUDING THE VOLTAGE-CONTROLLED DELAY LINES, AND MULTI-PHASE CLOCK GENERATORS USING THE VOLTAGE-CONTROLLED DELAY LINES A delay-locked loop circuit includes a voltage-controlled delay line configured to generate a plurality of delayed clock signals based on an input clock signal, a lock signal and a voltage control signal, the plurality of delayed clock signals being sequentially delayed...	12/08/2011
20110291722	PHASE CORRECTION CIRCUIT A phase correction circuit includes a skew detection unit configured to generate first skew detection signals and second skew detection signals by comparing multi-phase signals with one another, a phase control signal generation unit configured to generate a plurality o...	12/01/2011
20110291723	STREAM SIGNAL TRANSMISSION DEVICE AND TRANSMISSION METHOD Provided is a stream signal transmission device that can eliminate transmission delay fluctuation with a fast change such as network jitter with high accuracy and synchronize a plurality of streams. The stream signal transmission device includes at least one reception u...	12/01/2011
20110267117	DATA INPUT/OUTPUT APPARATUS AND METHOD FOR SEMICONDUCTOR SYSTEM A semiconductor memory device includes: a strobe signal reception unit configured to receive a strobe signal and generate a tracking clock signal; a clock reception unit configured to receive a clock signal and generate an internal clock signal; a plurality of data rece...	11/03/2011
20110249525	Circuits, Systems and Methods for Adjusting Clock Signals Based on Measured Performance Characteristics Circuits, systems, and related methods to measure a performance characteristic(s) associated with a semiconductor die and adjust a clock signal based on the measured performance characteristic(s) are provided. The adjusted clock signal can be used to provide a clock sig...	10/13/2011
20110248757	DIGITAL CALIBRATION DEVICE AND METHOD FOR HIGH SPEED DIGITAL SYSTEMS A digital calibration device and method for a high speed digital system. A digital calibration device coupled to a timing device in a high speed digital system for digitally calibrating the timing device includes a delay estimator, a control logic, and a digitally contr...	10/13/2011
20110241743	APPARATUS AND METHOD FOR SYNCHRONIZING TIMING CLOCK BETWEEN TRANSMISSION SIGNAL AND RECEPTION SIGNAL Provided are an apparatus and method for synchronizing a timing clock between a transmission signal and a reception signal. The apparatus for synchronizing a timing clock includes a timing restorer configured to restore a timing clock based on a digital input data; and ...	10/06/2011
20110228105	DATA TRANSFER DEVICE AND ELECTRONIC CAMERA A reception section receiving a reference signal and a data signal of data which is to be transferred, a holding section holding a test signal of test data received prior to the data and the reference signal, a calculation section calculating a delay amount which occurs...	09/22/2011
20110228165	SYNCHRONOUS SIGNAL CONVERSION CIRCUIT, SIGNAL PROCESSING SYSTEM INCLUDING IT, AND SYNCHRONOUS SIGNAL CONVERSION METHOD A synchronous signal conversion circuit converts a first synchronous signal, which is transmitted with a data signal, to a second synchronous signal conforming to a predetermined standard. In the synchronous signal conversion circuit, a transition detection circuit dete...	09/22/2011
20110221488	INTERFACE CIRCUIT WITH DAMPING RESISTOR CIRCUIT A semiconductor integrated circuit is provided with: a variable resistor section, a variable delay section and a data fetch section. The variable resistor section provides damping for a data signal inputted thereto to thereby generate a damped data signal. The damping r...	09/15/2011
20110221497	METHOD AND APPARATUS FOR MINIMIZING SKEW BETWEEN SIGNALS Delay associated with each of two signals along respective transmission paths is accurately measured using a delay measurement circuit that is fabricated in situ on the actual device where the circuitry for propagating the two signals is fabricated. Thus, the measured d...	09/15/2011
20110215852	HIGH SPEED LATCH CIRCUIT WITH METASTABILITY TRAP AND FILTER A synchronizer constituted of a first and second set of three serially coupled latches coupled to a common clocking signal, the first and the ultimate latch of the first set responsive to a first edge of a common clocking signal and the penultimate latch responsive to a...	09/08/2011
20110204946	SYSTEM AND METHOD FOR SYNCHRONIZING ASYNCHRONOUS SIGNALS WITHOUT EXTERNAL CLOCK One or more techniques are provided for the synchronization of asynchronous signals without the use of an external system clock. In one embodiment, an asynchronous synchronization device is provided and configured to synchronize one or more asynchronous signals to an in...	08/25/2011
20110193599	PHASE FREQUENCY TO DIGITAL CONVERTER A circuit arrangement is described comprising a first receiver configured to receive a first input signal, a second receiver configured to receive a second input signal, a first signal generator configured to generate a first pulse signal, a second signal generator conf...	08/11/2011
20110187429	SEMICONDUCTOR APPARATUS A semiconductor apparatus has a plurality of chips stacked therein. Read control signals for controlling read operations of the plurality of chips are synchronized with a reference clock such that the time taken from the application of a read command to the output of da...	08/04/2011
20110175656	CIRCUIT INCLUDING CURRENT-MODE LOGIC DRIVER WITH MULTI-RATE PROGRAMMABLE PRE-EMPHASIS DELAY ELEMENT A circuit (10) includes a circuit input (12), a circuit output (16) and a one or more delay elements (22) positioned between the circuit input (12) and the circuit output (16). The delay elements (22) each include a diffe...	07/21/2011
20110156757	INTER-PHASE SKEW DETECTION CIRCUIT FOR MULTI-PHASE CLOCK, INTER-PHASE SKEW ADJUSTMENT CIRCUIT, AND SEMICONDUCTOR INTEGRATED CIRCUIT An inter-phase skew detection circuit includes a frequency division circuit that frequency-divides N-phase clocks to be measured at predetermined timings so as to generate N+2 frequency-divided clocks; a phase comparison target clock generation circuit that generates N ...	06/30/2011
20110156785	TRIMMING OF A PSEUDO-CLOSED LOOP PROGRAMMABLE DELAY LINE An embodiment is proposed for trimming a programmable delay line in an integrated device, which delay line is adapted to delay an input signal being synchronous with a synchronization signal of the integrated device—by a total delay. An embodiment of a corresponding m...	06/30/2011
20110156784	CLOCK DELAY CORRECTING DEVICE AND SEMICONDUCTOR DEVICE HAVING THE SAME A semiconductor device includes an on-die termination circuit, a clock input unit, a clock phase mixing unit, and a data input/output unit. The on-die termination circuit is configured to calibrate a resistance of a termination pad and output an impedance matching code....	06/30/2011
20110148491	SEMICONDUCTOR APPARATUS AND LOCAL SKEW DETECTING CIRCUIT THEREFOR A local skew detecting circuit for a semiconductor apparatus include a reference delay block located on the center of the semiconductor apparatus, the reference delay block being configured to receive a predetermined signal and generate a reference delay signal by delay...	06/23/2011
20110131439	Jitter Precorrection Filter in Time-Average-Frequency Clocked Systems Synchronous circuitry for processing digital data in which the data are filtered to compensate for expected jitter in time-average frequency clock signals. Time-average frequency synthesis circuitry generates internal clock signals of a desired frequency, for example as...	06/02/2011
20110121875	POWER-MODE-AWARE CLOCK TREE AND SYNTHESIS METHOD THEREOF A power-mode-aware (PMA) clock tree and a synthesis method thereof are provided. The clock tree includes a sub clock tree and a PMA buffer. The sub clock tree transmits a delayed clock signal to a function module, wherein a power mode of the function module is determine...	05/26/2011
20110109360	SYSTEM AND METHOD FOR IMPROVED TIMING SYNCHRONIZATION Embodiments of a method and system for both open-loop and closed-loop timing synchronization are provided in which a master clock signal, and a plurality of signals that define greater periods of time, are distributed to a plurality of host devices. A frame-sync signal ...	05/12/2011
20110102037	CIRCUIT FOR RESETTING SYSTEM AND DELAY CIRCUIT A reset circuit and a delay circuit are provided. The delay circuit includes a first resistor module, a second resistor module, a switch module and a capacitor module. First terminals of the first and the second resistor modules are coupled respectively to a first volta...	05/05/2011
20110095797	SEMICONDUCTOR DEVICE AND METHOD FOR OPERATING THE SAME A semiconductor device includes a clock delay section configured to receive an external clock signal, reflect different delay amounts on the external clock signal, and generate a plurality of synchronization clock signals, a clock synchronization section configured to s...	04/28/2011
20110093235	SEMICONDUCTOR DEVICE A semiconductor device is provided. The semiconductor device applies data applied through a bump pad on which a bump is mounted through a test pad to a test apparatus such that the reliability of the test can be improved. The amount of test pads is significantly reduced...	04/21/2011
20110089984	Clock signal balancing circuit and method for balancing clock signal in IC layout A method for balancing clock signals in an IC layout includes obtaining a data-flow information of the IC, selecting a first data-flow according to the dataflow information, and synchronizing a first clock signal from a first register and a second clock signal from a se...	04/21/2011
20110089985	Delay Line Calibration Mechanism and Related Multi-Clock Signal Generator A delay line calibration mechanism includes a first delay line, a second delay line, a phase detector, and a controller. The first delay line receives a first pulse and a first delay selection signal, and delays the first pulse for a first delay period according to the ...	04/21/2011
20110084744	Semiconductor device, adjustment method thereof and data processing system Read data that are output from core chips are accurately captured into an interface chip. Each of the core chips includes a data output circuit that outputs read data to the interface chip in response to a read command, and an output timing adjustment circuit that adjus...	04/14/2011
20110057698	METHOD AND APPARATUS FOR SYNCHRONIZING WITH A CLOCK SIGNAL Clock synchronization and skew adjustment circuits that utilize differing unit delay elements in their delay lines in either a graduated or a stepped unit time delay arrangement are for synchronizing with a clock signal. These graduated or a stepped unit time delays all...	03/10/2011
20110057699	INTEGRATED CIRCUIT AND PROGRAMMABLE DELAY Integrated circuit and programmable delay. One embodiment provides an integrated circuit including a programmable delay element having a plurality of single delay cells. The delay cells include a first input and a second input and a first output. The delay cells are arr...	03/10/2011

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Class 327/161 - With delay means