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| Application No. | Application Title | Issue Date |
| 20120126867 | SIGNAL PATTERN AND DISPERSION TOLERANT STATISTICAL REFERENCE OSCILLATOR Disclosed is a statistical reference oscillator that includes: a stochastic reference clock generator which receives an input data outputs a reference signal obtained by dividing the received input data at a first frequency division ratio; a frequency divider which divi... | 05/24/2012 |
| 20120105116 | FREQUENCY SYNTHESIZER There is provided a frequency synthesizer. The frequency synthesizer includes a frequency oscillator adjusting an output frequency according to a control bit; a programmable divider having a preset minimum division ratio, the programming divider dividing the output freq... | 05/03/2012 |
| 20120105117 | Phase-Lock Loop A phase-lock loop having a reduced lock time in comparison with the conventional art. The phase-lock loop compares an output signal thereof with a reference signal, and alters a control signal in response thereto such that the output signal may have a desired frequency.... | 05/03/2012 |
| 20120105110 | Signal level adjusting device and high-frequency apparatus To provide, in a frequency synthesizer including: a variable attenuator provided at a subsequent stage of a voltage controlled oscillator; a detector; and a control unit outputting a control voltage for adjusting an attenuation amount of the variable attenuator via a di... | 05/03/2012 |
| 20120105114 | SPREAD SPECTRUM CLOCK GENERATING CIRCUIT Provided is a spread spectrum clock generating circuit. The spread spectrum clock generating circuit includes: a phase detector receiving a reference frequency signal from the external and detecting a phase difference between the reference frequency signal and a frequen... | 05/03/2012 |
| 20120105115 | CLOCK AND DATA RECOVERY CIRCUIT A clock and data recovery circuit includes a multiphase clock generator circuit which generates a multiphase clock having a plurality of clocks, a sampling circuit which samples a received data signal transferring serial data in synchronism with each of the plurality of... | 05/03/2012 |
| 20120109356 | Method and Digital Circuit for Recovering a Clock and Data from an Input Signal Using a Digital Frequency Detection In a particular embodiment, a digital circuit includes a frequency detection circuit operative to compare information related to transitions between sequential samples of a received signal. The frequency detection circuit is further operative to generate a control signa... | 05/03/2012 |
| 20120081339 | DIGITAL PLL CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT, AND DISPLAY APPARATUS In a digital PLL circuit, a phase comparison circuit counts the numbers of transitions of a reference clock and an oscillation clock, sets a time taken until the number of transitions of the reference clock reaches a reference count value as a phase comparison time peri... | 04/05/2012 |
| 20120081158 | REFERENCE CLOCK SAMPLING DIGITAL PLL A digital phase locked loop (DPLL) operates in the frequency domain. The period (and hence frequency) of a reference frequency clock signal is determined by sampling with a (higher frequency) digitally controlled oscillator (DCO) clock. The period is compared to the per... | 04/05/2012 |
| 20120081159 | METHOD USING DIGITAL PHASE-LOCKED LOOP CIRCUIT INCLUDING A PHASE DELAY QUANTIZER A phase locked loop circuit and method for use, in accordance with an embodiment, implements a digital phase delay quantizer to replace the analog charge-pump and phase frequency detector in an analog PLL circuit. Therefore, the built-in loop filter can be a compact-siz... | 04/05/2012 |
| 20120068742 | METHOD AND APPARATUS FOR EFFICIENT TIME SLICING Apparatus for efficient time slicing including a phase lock loop circuit having a voltage controlled oscillator, an auto-frequency calibration circuit coupled with the phase lock loop circuit configured to output a value to select a range of the voltage controlled oscil... | 03/22/2012 |
| 20120068743 | Feedback-Based Linearization of Voltage Controlled Oscillator Embodiments of the present invention enable a feedback-based VCO linearization technique. Embodiments include a frequency locked loop formed by feeding back a VCO's output into the VCO's input in negative phase by means of a frequency-to-voltage (F/V) converter. Embodim... | 03/22/2012 |
| 20120068744 | Phase Locked Loop Circuits A phase locked loop circuit is provided. The PLL circuit receives an input clock signal and generates an output clock signal according to internal clock signals with phase shifting which are generated according to the input clock signal. The PLL circuit includes a selec... | 03/22/2012 |
| 20120049909 | TRANSCEIVER SYSTEM HAVING PHASE AND FREQUENCY DETECTOR AND METHOD THEREOF A transceiver system having a phase and frequency locked architecture is described. The transceiver system includes a clock and data recovery type receiver, a frequency divider and a transmitter. The clock and data recovery type receiver receives an external signal from... | 03/01/2012 |
| 20120049912 | DIGITAL PHASE DIFFERENCE DETECTOR AND FREQUENCY SYNTHESIZER INCLUDING THE SAME A digital phase difference detector detects a phase difference between first and second signals. A delay circuit cumulatively delays the first signal. A flip flop group latches the signals. An edge detector detects a first phase difference between a rise of the first si... | 03/01/2012 |
| 20120049910 | Semiconductor device A semiconductor device includes a clock-and-data recovery circuit including a phase tracking loop that generates a phase difference signal indicating a phase difference between a reception clock generated from a transmission clock and an input signal and makes the recep... | 03/01/2012 |
| 20120049913 | VOLTAGE-CONTROLLED OSCILLATOR AND GAIN CALIBRATION TECHNIQUE FOR TWO-POINT MODULATION IN A PHASE-LOCKED LOOP A VCO in a phase-locked loop (PLL) is arranged to receive low-pass data via a first input and high-pass data at a second input. The first input is coupled to a first set of varactors in the VCO. The second input is coupled to a second set of varactors in the VCO. The co... | 03/01/2012 |
| 20120049911 | Clock Generation Circuit A clock generation circuit includes a first divider, a loop unit that has a second divider and generates an output clock which is in phase synchronization with a reference clock of the first divider and has a frequency that is F times the reference clock, a clock switch... | 03/01/2012 |
| 20120047481 | IMPLEMENTING PHASE LOCKED LOOP (PLL) WITH ENHANCED LOCKING CAPABILITY WITH A WIDE RANGE DYNAMIC REFERENCE CLOCK A method and a phase locked loop (PLL) circuit for implementing enhanced locking capability with a wide range dynamic reference clock, and a design structure on which the subject circuit resides are provided. The PLL circuit includes a Voltage Controlled Oscillator (VCO... | 02/23/2012 |
| 20120044001 | SIGNAL PROCESSING APPARATUS A signal processing apparatus of the present invention includes an input unit configured to receive a reference signal supplied from an external device, a phase detection unit configured to detect a phase difference between the reference signal received from the input u... | 02/23/2012 |
| 20120044000 | Method and Apparatus for Accurate Clock Synthesis Methods and apparatus are provided in the present invention to adjust the frequency of an output clock close to within a required accuracy of an oscillation frequency. In another embodiment, a method comprises: entering a calibration mode; generating a first control wor... | 02/23/2012 |
| 20120038401 | METHOD OF COMPENSATING AN OSCILLATION FREQUENCY AND PLL A method for compensating an oscillation frequency, a device, and a phase locked loop (PLL) is applied in the LC oscillating loop, including: sending voltage control signals to one end of a variable capacitor of an LC oscillating loop to generate oscillating signals in ... | 02/16/2012 |
| 20120038400 | METHOD AND APPARATUS FOR JITTER REDUCTION A low bandwidth phase lock loop (PLL) arranged in a dual-loop configuration is disclosed. The first loop is a standard loop configuration using a crystal oscillator as a reference clock. The loop parameters for this first PLL can be optimized to work over a wide range o... | 02/16/2012 |
| 20120032718 | Digital Phase Lock System with Dithering Pulse-Width-Modulation Controller A Digital Phase-Locked Loop (DPLL) has a digitally-controlled oscillator (DCO) that generates an output clock frequency determined by a digital input with most-significant-bits (MSB's) and a least-significant-bit (LSB). The LSB is generated by a Pulse-Width-Modulation (... | 02/09/2012 |
| 20120025879 | PLL CIRCUIT, METHOD FOR OPERATING PLL CIRCUIT AND SYSTEM A PLL circuit includes: a first counter to accumulate a frequency command word in response to a reference clock signal and to generate a first counted value; a second counter to count an output clock signal and generate a second counted value; a time measuring circuit t... | 02/02/2012 |
| 20120025919 | Synchronization of multiple high frequency switching power converters in an integrated circuit A phase locked loop is used to synchronize the switching frequency of a high frequency switching power converter to a clock signal. A switching power converter integrated circuit is a tile-based power management unit and includes an oscillator and multiple tiles of swit... | 02/02/2012 |
| 20120025880 | Fractional Spur Reduction Using Controlled Clock Jitter In one embodiment, an apparatus includes a jitter generator configured to receive a reference clock; add jitter to the reference clock; and output the reference clock with the included jitter to a phase lock loop (PLL). The PLL is used to generate a local oscillator (LO... | 02/02/2012 |
| 20120025882 | CALIBRATION FOR PHASE-LOCKED LOOP A method for calibrating a bandwidth of a phase-locked loop begins with detecting an error signal generated by the phase-locked loop in response to a stimulus signal. The difference between the integral of the error signal and a nominal value thereof is computed, and th... | 02/02/2012 |
| 20120019293 | DELAY LOCK LOOP PHASE GLITCH ERROR FILTER A method and apparatus is provided for providing a phase glitch error filter for a delay lock loop. The device comprises a delay lock loop to provide an output signal based upon a phase difference between a reference signal and a feedback signal. The delay lock loop com... | 01/26/2012 |
| 20120013376 | USE OF PLL STABILITY FOR ISLANDING DETECTION A phase detector for a phase-locked loop includes a phase detector that is configured to become unstable, oscillate and drift rapidly in frequency in a predictable manner when a reference frequency signal is not available. When applied, for example, to a power converter... | 01/19/2012 |
| 20120013343 | RECEIVING APPARATUS, TEST APPARATUS, RECEIVING METHOD, AND TEST METHOD A receiving apparatus that acquires a reception signal using a recovered clock that is recovered from an edge of the reception signal. The receiving apparatus comprises a recovered clock generating section that generates the recovered clock; a multi-strobe generating se... | 01/19/2012 |
| 20120013375 | FREQUENCY SYNTHESIZER DEVICE AND MODULATION FREQUENCY DISPLACEMENT ADJUSTMENT METHOD A frequency synthesizer device that includes two modulation paths and suitably adjusts the amplitude of a control voltage that is outputted from a digital-to-analog converter (DAC) to a voltage-controlled oscillator. The frequency synthesizer device is provided with a v... | 01/19/2012 |
| 20120013498 | EXPANDABLE AND RECONFIGURABLE INSTRUMENT NODE ARRAYS An expandable and reconfigurable instrument node includes a feature detection means and a data processing portion in communication with the feature detection means, the data processing portion configured and disposed to process feature information. The instrument node f... | 01/19/2012 |
| 20120007640 | Multi-Channel Multi-Protocol Transceiver With Independent Channel Configuration Using Single Frequency Reference Clock Source A circuit for producing one of a plurality of output clock frequencies from a single, constant input reference clock frequency. The circuit comprises a reference clock system and a phase lock loop. The reference clock system includes a bypass path, a divider path includ... | 01/12/2012 |
| 20120007642 | REFERENCE FREQUENCY GENERATING DEVICE The disclosed is a reference frequency generating device (11), which includes a GPS receiver (21), a PLL circuit (31), a detector (28), a memory unit (29), and a controller (22). The PLL circuit (31) controls the digitall... | 01/12/2012 |
| 20120007641 | ELECTRONIC PART AND METHOD OF DETECTING FAULTS THEREIN An electronic component includes an oscillator element, a driving circuit outputting a driving signal to the oscillator element, a clock frequency generator outputting a clock signal to the driving circuit, a clock frequency controller controlling a frequency of the clo... | 01/12/2012 |
| 20120002707 | PLL FREQUENCY SYNTHESIZER A PLL frequency synthesizer includes: a phase comparator configured to detect a phase difference between a reference clock signal and an output signal of the PLL frequency synthesizer; a loop filter configured to output a control value composed of a total of an integer ... | 01/05/2012 |
| 20110316595 | VCO FREQUENCY TEMPERATURE COMPENSATION SYSTEM FOR PLLS The present invention discloses a continuous voltage controlled oscillator (VCO) frequency temperature compensation apparatus for a phase locked loop (PLL) and a continuous VCO frequency temperature compensation method for a PLL. The system utilizes a VCO with one digit... | 12/29/2011 |
| 20110316597 | SIGNAL GENERATOR WITH OUTPUT FREQUENCY GREATER THAN THE OSCILLATOR FREQUENCY Systems and methods for design and operation of signal generator circuitry with output frequencies greater than the oscillator frequency. Accordingly, in a first method embodiment, a method of producing an output periodic electronic signal comprises accessing four signa... | 12/29/2011 |
| 20110316596 | PHASE LOCKING FOR MULTIPLE SERIAL INTERFACES An arrangement is described which reduces the number of phase locked loops (PLLs) required in a typical high speed serial interface system. A reference clock is sent from a transmitter on a main board to a receiver on a system board, which employs a PLL that also drives... | 12/29/2011 |
