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| Application No. | Application Title | Issue Date |
| 20120038386 | LATCH CIRCUIT A latch circuit includes a feedback circuit having inverter circuits and at least two input terminals and an input circuit for inputting input signals or signals having the same phase as the input signals to the input terminals of the feedback circuit in synchronization... | 02/16/2012 |
| 20110309856 | METHOD AND APPARATUS FOR REDUCING RADIATION AND CROSS-TALK INDUCED DATA ERRORS The different advantageous embodiments provide an integrated circuit comprising a number of latches and a number of filters. Each latch in the number of latches has a plurality of inputs and a plurality of storage nodes. The plurality of storage nodes includes a number ... | 12/22/2011 |
| 20110298490 | ASYMMETRICAL AGING CONTROL SYSTEM An asymmetrical aging control system is described. This system actively varies associated dedicated circuits in a manner that minimizes power consumption, while preventing asymmetrical aging.... | 12/08/2011 |
| 20110260750 | Fault Tolerant Integrated Circuit Architecture The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface... | 10/27/2011 |
| 20110128035 | CLOSED-LOOP SOFT ERROR RATE SENSITIVITY CONTROL Disclosed is a closed-loop feedback system for controlling the soft error rate (SER) due to radiation strikes on electronic circuitry. A variable sensitivity soft error rate detector provides and output corresponding to the soft error rate. This output is supplied to a ... | 06/02/2011 |
| 20110057683 | DEFECT-AND-FAILURE-TOLERANT DEMULTIPLEXER USING SERIES REPLICATION AND ERROR-CONTROL ENCODING One embodiment of the present invention is a method for constructing defect-and-failure-tolerant demultiplexers. This method is applicable to nanoscale, microscale, or larger-scale demultiplexer circuits. Demultiplexer circuits can be viewed as a set of AND gates, each ... | 03/10/2011 |
| 20110025372 | METHOD AND APPARATUS FOR REDUCING RADIATION AND CROSS-TALK INDUCED DATA ERRORS The different advantageous embodiments provide an integrated circuit comprising a number of latches and a number of filters. Each latch in the number of latches has a plurality of inputs and a plurality of storage nodes. The plurality of storage nodes includes a number ... | 02/03/2011 |
| 20110006803 | LATCH CIRCUIT A latch circuit includes a feedback circuit having inverter circuits and at least two input terminals and an input circuit for inputting input signals or signals having the same phase as the input signals to the input terminals of the feedback circuit in synchronization... | 01/13/2011 |
| 20100321058 | Fault Tolerant Integrated Circuit Architecture The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface... | 12/23/2010 |
| 20100283502 | ASYNCHRONOUS NANO-ELECTRONICS Asynchronous nanoelectronic circuits that operate according to principles of quasi-delay insensitive design are described. Circuit or logic elements comprising n-type devices are fabricated in a first n-plane, p-type devices are fabricated in a p-plane, and connections ... | 11/11/2010 |
| 20100244889 | Resilient Integrated Circuit Architecture The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface... | 09/30/2010 |
| 20100207658 | FAULT TOLERANT ASYNCHRONOUS CIRCUITS New and improved methods and circuit designs for asynchronous circuits that are tolerant to transient faults, for example of the type introduced through radiation or, more broadly, single-event effects. SEE-tolerant configurations are shown and described for combination... | 08/19/2010 |
| 20100079164 | Systems and Methods for Improving the PN Ratio of a Logic Gate by Adding a Non-Switching Transistor Systems and methods for improving a PN ratio of a logic gate by adding a non-switching transistor. In one embodiment, the logic gate includes a plurality of PMOS switching transistors and a plurality of NMOS switching transistors that are switched on and off by received... | 04/01/2010 |
| 20100039135 | SEMICONDUCTOR INTEGRATED CIRCUIT Semiconductor integrated circuit has a control circuit. The control circuit causes the clock signal generating circuit to control the first clock signal and the second clock signal to make a logic of data held by the first data holding terminal and a logic of data held ... | 02/18/2010 |
| 20100033207 | Fault Tolerant Integrated Circuit Architecture The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface... | 02/11/2010 |
| 20100008155 | Structurally field-configurable semiconductor array for in-memory processing of stateful, transaction-oriented systems A semiconductor memory device is provided. The semiconductor memory device includes a plurality of memory cells arranged in multiple column groups, each column group having, a plurality of columns and a plurality of external bit-lines for independent multi-way configura... | 01/14/2010 |
| 20090309627 | Methodology and Apparatus for Reduction of Soft Errors in Logic Circuits The present invention includes a circuit-level system and method for preventing the propagation of soft errors in logic cells. A radiation jammer circuit in accordance with the present invention, including an RC differentiator and a depletion mode MOS circuit, when inse... | 12/17/2009 |
| 20090302884 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND COUNTERMEASURE METHOD AGAINST NBTI DEGRADATION A semiconductor integrated circuit device includes a target circuit of a low power consumption mode having at least one flip-flop circuit to which a clock signal is supplied in a normal operation mode and in a low power consumption mode, and a logic circuit to which eac... | 12/10/2009 |
| 20090302883 | Device forming a logic gate for detecting a logic error The invention relates to a device for forming an electric circuit comprising logic means (30) generating and using small signals of intermediate levels between the device supply levels and means for detecting signals leaving the small signal range.... | 12/10/2009 |
| 20090289657 | SYSTEMS AND METHODS FOR PROVIDING DEFECT-TOLERANT LOGIC DEVICES The present invention describes systems and methods to provide defect-tolerant logic devices. An exemplary embodiment of the present invention provides a defect-tolerant logic device including a plurality of CMOS gates and at least one defective CMOS gate included withi... | 11/26/2009 |
| 20090278564 | RECONFIGURABLE INTEGRATED CIRCUIT AND METHOD FOR INCREASING PERFORMANCE OF A RECONFIGURABLE INTEGRATED CIRCUIT Methods are disclosed to increase yielded performance of a reconfigurable integrated circuit; improve performance of an application running on a reconfigurable integrated circuit; reduce degradation of an integrated circuit over time; and maintain performance of an inte... | 11/12/2009 |
| 20090230988 | ELECTRONIC DEVICE HAVING LOGIC CIRCUITRY AND METHOD FOR DESIGNING LOGIC CIRCUITRY An electronic device with logic circuitry (LC) is provided. The logic circuitry (LC) comprises at least one electronic unit (EU), in particular one logic gate with a first electronic component (EC1) for performing logic operations; and at least one second electro... | 09/17/2009 |
| 20090219752 | Apparatus and Method for Improving Storage Latch Susceptibility to Single Event Upsets An apparatus for improving storage latch susceptibility to single event upsets includes a dual interconnected storage cell (DICE) configured within a storage latch circuit; a pair of separate three-state circuits configured to write the DICE latch, with each three-state... | 09/03/2009 |
| 20090213946 | PARTIAL RECONFIGURATION FOR A MIMO-OFDM COMMUNICATION SYSTEM Partial reconfiguration of programmable logic for supporting a Multiple-input, Multiple-Output Orthogonal Frequency Division Multiplexing (“MIMO-OFDM”) communication system is described. A PHY block in a programmable device may be instantiated generally in part in p... | 08/27/2009 |
| 20090206872 | SYSTEM, METHOD AND APPARATUS FOR ENHANCING RELIABILITY ON SCAN-INITIALIZED LATCHES AFFECTING FUNCTIONALITY A system, method, and apparatus for enhancing reliability on scan-initialized latches that affect functionality in a digital design are provided. The system includes a group of latches that affect functionality in the digital design based on state values of the latches,... | 08/20/2009 |
| 20090201044 | LOGIC PERFORMANCE IN CYCLIC STRUCTURES Apparatus, systems, and methods may operate to identify state holding elements and functional logic elements in an original cyclic structure, and to insert additional state holding elements or initial tokens in series with the identified functional logic elements to cre... | 08/13/2009 |
| 20090189634 | SINGLE EVENT TRANSIENT MITIGATION AND MEASUREMENT IN INTEGRATED CIRCUITS A method for single event transient filtering in an integrated circuit device is described. The device comprises three sequential elements, each having a data input and a data output with each of the three data outputs coupled to one of three inputs of a voting gate. Th... | 07/30/2009 |
| 20090140764 | Latch Circuit A latch circuit includes a feedback circuit having inverter circuits and at least two input terminals and an input circuit for inputting input signals or signals having the same phase as the input signals to the input terminals of the feedback circuit in synchronization... | 06/04/2009 |
| 20090135643 | SEU HARDENING CIRCUIT AND METHOD An SEU hardening circuit and method is disclosed. In one embodiment, a method includes providing a semiconductor memory component having a pair of pMOS transistors and a pair of nMOS transistors, tying a first pMOS body terminal of a first pMOS transistor of the pair of... | 05/28/2009 |
| 20090134907 | Fault Tolerant Integrated Circuit Architecture The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface... | 05/28/2009 |
| 20090134906 | Resilient Integrated Circuit Architecture The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface... | 05/28/2009 |
| 20090115447 | Design Structure for an Integrated Circuit Having State-Saving Input-Output Circuitry and a Method of Testing Such an Integrated Circuit A design structure for an integrated circuit that includes input/output (I/O) state saving circuitry capable of stabilizing the I/O states during any predicted I/O disturbance event. The I/O state saving circuitry includes a plurality of transparent latches arranged bet... | 05/07/2009 |
| 20090108866 | RADIATION HARDENED LOGIC CIRCUITS A radiation hardened inverter includes first and second electrical paths between an input terminal and an output terminal. A first PFET is disposed in the first electrical path, and a bipolar junction transistor (BJT) is disposed in the second electrical path. The first... | 04/30/2009 |
| 20090102506 | ADAPTER An exemplary adapter comprises an input port for connecting to a first hardware device; an output port for connecting to a second hardware device; a standby output port for connecting to the second hardware device; a programmable logic device (PLD) having at least one i... | 04/23/2009 |
| 20090051385 | Cell with Fixed Output Voltage for Integrated Circuit The invention relates to a testable integrated circuit. In order to replace ground and VDD in certain points of such a circuit, the circuit comprises a cell (34) which comprises a flipflop (11) and means (31) able to set the output voltage of the ce... | 02/26/2009 |
| 20090027078 | FAULT TOLERANT ASYNCHRONOUS CIRCUITS New and improved methods and circuit designs for asynchronous circuits that are tolerant to transient faults, for example of the type introduced through radiation or, more broadly, single-event effects. SEE-tolerant configurations are shown and described for combination... | 01/29/2009 |
| 20090002015 | ERROR CORRECTING LOGIC SYSTEM The invention includes an error correcting logic system that allows critical circuits to be hardened with only one redundant unit and without loss of circuit performance. The system provides an interconnecting gate that suppresses a fault in one of at least two redundan... | 01/01/2009 |
| 20080297191 | APPARATUS AND METHOD OF ERROR DETECTION AND CORRECTION IN A RADIATION-HARDENED STATIC RANDOM ACCESS MEMORY FIELD-PROGRAMMABLE GATE ARRAY The present system comprises a radiation tolerant programmable logic device having logic modules and routing resources coupling together the logic modules. Configuration data lines providing configuration data control the programming of the logic modules and the routing... | 12/04/2008 |
| 20080256343 | Convergence determination and scaling factor estimation based on sensed switching activity or measured power consumption A method and system for determining convergence of iterative processes and estimating a scaling factor in decoding processes based on switching activity of the logic circuitry are provided. During execution of an iterative process using logic circuitry comprising logic ... | 10/16/2008 |
| 20080191733 | CONFIGURABLE IC WITH TRACE BUFFER AND/OR LOGIC ANALYZER FUNCTIONALITY Some embodiments of the invention provide a configurable integrated circuit (IC) that includes several configurable circuits for configurably performing different operations and several user design state (UDS) circuits for storing user-design state values. The IC furthe... | 08/14/2008 |
