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| Application No. | Application Title | Issue Date |
| 20110234259 | OPPORTUNISTIC BUS ACCESS LATENCY A bus system that includes a plurality of signal driving devices coupled to a common signal bus, a bus controlled circuit coupled to the common signal bus, and a compare circuit. The plurality of signal driving devices include a first signal driving device and a second ... | 09/29/2011 |
| 20110204922 | Receiver to Match Delay for Single Ended and Differential Signals In one embodiment, a receiver circuit is provide that may receive either a differential input or a single-ended input corresponding to an interface. The receiver circuit may include at least two current sources to control a gain of an amplification stage in the receiver... | 08/25/2011 |
| 20110199120 | SEMICONDUCTOR INTEGRATED CIRCUIT A semiconductor integrated circuit capable of reducing unnecessary current consumption includes a plurality of bus drive circuits for receiving data input, a common bus coupled to the bus drive circuits, and a bus holder coupled to the common bus. One of the bus drive c... | 08/18/2011 |
| 20100207661 | BI-DIRECTIONAL BUFFER FOR OPEN-DRAIN OR OPEN-COLLECTOR BUS Provided herein are bi-directional buffers, and methods for providing bi-directional buffering. In an embodiment, a bi-directional buffer includes a differential input/differential output amplifier that includes a first input/output node and a second/input output node. ... | 08/19/2010 |
| 20100164546 | CIRCUIT SYSTEM INCLUDING FIRST CIRCUIT SUB-SYSTEM, SECOND CIRCUIT SUB-SYSTEM AND BIDIRECTIONAL BUS, CIRCUIT SUB-SYSTEM AND METHOD A circuit system has a first and a second circuit sub-system, and a bidirectional bus, the first circuit sub-system having a first control circuit that receives a control signal for controlling the direction of the bidirectional bus, and controls the first sub-system to... | 07/01/2010 |
| 20100102853 | Circuitry and Methods Minimizing Output Switching Noise Through Split-Level Signaling and Bus Division Enabled by a Third Power Supply Disclosed herein are circuitry and methods for transmitting data across a parallel bus using both high common mode and low common mode signaling. The transmitter stages are configured to work with two of three possible power supply voltages: a high Vddq voltage, a low V... | 04/29/2010 |
| 20100066410 | LOW-LOSS IMPEDANCE-MATCHED SOURCE-FOLLOWER FOR REPEATING OR SWITCHING SIGNALS ON A HIGH SPEED LINK Switching and repeating applications using an impedance matched source follower improve performance of high speed links such as PCI Express, HDMI, DisplayPort and DVI by reducing attenuation and other degradation of high speed signals, including those with transmit pre-... | 03/18/2010 |
| 20100045339 | WIRELINE TRANSMISSION CIRCUIT A wireline transmission circuit includes a first circuit that produces a first variable current, a second circuit that produces a first static current, a trans-impedance amplifier that outputs a first analog signal at a first output node in response to the first variabl... | 02/25/2010 |
| 20090323830 | CURRENT MODE CIRCUITRY TO MODULATE A COMMON MODE VOLTAGE In some embodiments, a chip includes transmitters to transmit differential signals on conductors; and current mode circuitry to selectively modulate a common mode voltage of the differential signals to communicate data. In other embodiments, a system includes a first ch... | 12/31/2009 |
| 20090309631 | CIRCUIT WITH ENHANCED MODE AND NORMAL MODE Circuit with enhanced mode and normal mode is provided and described. In one embodiment, switches are set to a first switch position to operate the circuit in the enhanced mode. In another embodiment, switches are set to a second switch position to operate the circuit i... | 12/17/2009 |
| 20090289662 | BRIDGE DESIGN FOR SD AND MMC DATA BUSES A circuit with bi-directional signal transmission, including a first signal source, for generating a first signal comprising one bit per clock cycle during a first plurality of clock cycles, a second signal source, for generating a second signal including one bit per cl... | 11/26/2009 |
| 20090278251 | Pad Structure for 3D Integrated Circuit This invention discloses an I/O pad structure in an integrated circuit (IC) which comprises a first vertical region in the IC including a top metal layer and one or more semiconductor devices formed thereunder, the top metal layer in the first vertical region serving as... | 11/12/2009 |
| 20090273369 | GTL BACKPLANE BUS WITH IMPROVED RELIABILITY Isolation components such as p-n junction or Schottky diodes are provided at pull-up resistors of each signal line of a Gunning Transceiver Logic (GTL) backplane bus in an electronic system for improved reliability, specifically to prevent momentary termination of the b... | 11/05/2009 |
| 20090179668 | BRIDGE DESIGN FOR SD AND MMC MULTIPLEXING A method for determining direction of signal transmission in a bi-directional signal line, including sampling data signals at two terminals, A and B, enabling data flow from A to B when data flow from B to A is not enabled, and a logical 0 bit is sampled at A, enabling ... | 07/16/2009 |
| 20090153192 | BI-DIRECTIONAL BUFFER FOR OPEN-DRAIN OR OPEN-COLLECTOR BUS Provided herein are bi-directional buffers, and methods for providing bi-directional buffering. In an embodiment, a bi-directional buffer includes a differential input/differential output amplifier that includes a first input/output node and a second/input output node. ... | 06/18/2009 |
| 20090146684 | CIRCUIT FOR CONTROLLING DRIVER OF SEMICONDUCTOR MEMORY APPARATUS AND METHOD OF CONTROLLING THE SAME A circuit for controlling a driver of a semiconductor memory apparatus includes a driving unit having an impedance that is set according to a code value; a driving reinforcing control unit configured to output an adjustment code for a predetermined time; and a driving r... | 06/11/2009 |
| 20090140772 | ARCHITECTURE FOR VBUS PULSING IN UDSM PROCESSES Architecture for VBUS pulsing in an Ultra Deep Sub Micron (UDSM) process for ensuring USB-OTG (On The Go) session request protocol, the architecture being of the type wherein at least a charging circuit is deployed, uses a diode-means connected in a forward path of the ... | 06/04/2009 |
| 20090102513 | Low Power Output Driver A low power output driver includes one of a regulated reduced voltage source that receives a supply voltage and outputs a regulated reduced voltage that is a lower voltage than the supply voltage. The driver also includes a first driver input that receives a first logic... | 04/23/2009 |
| 20090085608 | Systems, methods and devices for arbitrating die stack position in a multi-bit stack device Embodiments are described for arbitrating stacked dies in multi-die semiconductor packages. In one embodiment, die identification data for at least two stacked dies are arbitrated to select one of the dies as the primary die and the other as secondary. Each die includes... | 04/02/2009 |
| 20090072861 | WIRELINE TRANSMISSION CIRCUIT A wireline transmission circuit includes a first circuit that produces a first variable current, a second circuit that produces a first static current, a trans-impedance amplifier that outputs a first analog signal at a first output node in response to the first variabl... | 03/19/2009 |
| 20090045845 | Adjusting Output Buffer Timing Based on Drive Strength This invention operates to select a drive code for an adjustable drive strength transistor in a drive buffer. The drive code is determined employing a scaled-down drive transistor employing varying drive codes compared with a standard. The thus determined drive code is ... | 02/19/2009 |
| 20090045846 | ADVANCED REPEATER WITH DUTY CYCLE ADJUSTMENT An advanced repeater with duty cycle adjustment. In accordance with a first embodiment of the present invention, an advanced repeater includes an output stage for driving an output signal line responsive to an input signal and a plurality of active devices for selectabl... | 02/19/2009 |
| 20090033366 | DATA TRANSMISSION SYSTEM AND CABLE A data transmission system capable of transmitting data at high speed without being bound by a counterpart's power supply voltage can be realized. The data transmission system comprises multiple electronic equipment having individual power supplies, a cable for connecti... | 02/05/2009 |
| 20090015289 | SIGNAL TRANSMITTING DEVICE SUITED TO FAST SIGNAL TRANSMISSION A signal transmitting circuit includes a circuit block having a driving circuit and an intra-block transmission line for transmitting a signal from the driving circuit, a circuit block having a receiving circuit and an intra-block transmission line for transmitting the ... | 01/15/2009 |
| 20080278193 | Reference voltage generators for reducing and/or eliminating termination mismatch A system including a plurality of transmission lines, a transmitter outputting respective signals to each of the plurality of transmission lines, a receiver receiving each of the plurality of signals via respective transmission lines, the receiver including a connection... | 11/13/2008 |
| 20080265944 | Output Buffer Circuit and Differential Output Buffer Circuit, and Transmission Method In an output buffer circuit including Inverter 1 to Inverter 3, Delay Circuit 1 to Delay Circuit 3 for delaying an input signal for a specific time, Buffer 1 to Buffer 3, and a function for transmitting a logic signal to a trans... | 10/30/2008 |
| 20080258765 | Low-power transceiver architectures for programmable logic integrated circuit devices High-speed serial interface or transceiver circuitry on a programmable logic device integrated circuit (“PLD”) includes features that permit the PLD to satisfy a wide range of possible user needs or applications. This range includes both high-performance application... | 10/23/2008 |
| 20080218215 | Advanced Repeater Utilizing Signal Distribution Delay An advanced repeater utilizing signal distribution delay. In accordance with a first embodiment of the present invention, such an advanced repeater circuit comprises an output stage for driving an output signal line responsive to an input signal and a feedback loop coup... | 09/11/2008 |
| 20080204070 | Reduced power output buffer A clock driving circuit and a method of driving a plurality of output lines for a PC architecture are disclosed. The clock driving circuit includes a clock generating circuit coupled to an output buffer for the PC having a plurality of output lines connected to a plural... | 08/28/2008 |
| 20080169840 | Semiconductor device having a pseudo power supply wiring A semiconductor device including an AND-NOR composite gate of which AND unit is supplied with input signals IN and VDD and NOR unit is supplied with an inverted signal EB of an enable signal E, and an AND-NOR composite gate of which AND unit is supplied with an input si... | 07/17/2008 |
| 20080129341 | SEMICONDUCTOR APPARATUS A semiconductor apparatus that is effective for problems of local characteristic variations and that enables higher speed and lower power consumption. Semiconductor apparatus 100 has: a plurality of sensor circuits 101a to 101g which a... | 06/05/2008 |
| 20080122489 | COMMUNICATION INTERFACE EMPLOYING A DIFFERENTIAL CIRCUIT AND METHOD OF USE A communication interface employing a differential circuit and method of use is disclosed. In one form, a circuit operable to communicate signals via a communication bus can include a differential signaling circuit operable to be coupled to a communication bus. The diff... | 05/29/2008 |
| 20080088343 | Repeater circuit with high performance repeater mode and normal repeater mode, wherein high performance repeater mode has fast reset capability Repeater circuit with high performance repeater mode and normal repeater mode, wherein high performance repeater mode has fast reset capability, is provided and described. In one embodiment, switches are set to a first switch position to operate the repeater circuit in ... | 04/17/2008 |
| 20080048724 | LOW POWER OUTPUT DRIVER A low power output driver includes one of a regulated reduced voltage source that receives a supply voltage and outputs a regulated reduced voltage that is a lower voltage than the supply voltage. The driver also includes a first driver input that receives a first logic... | 02/28/2008 |
| 20070262791 | Integrated Circuit to Store a Datum An integrated circuit includes a programmable circuit with a programmable element, and a storage circuit to store a storage state depending on a programming state of the programmable element of the programmable circuit unit. The storage circuit includes a first inverter... | 11/15/2007 |
| 20070216446 | Complementary output inverter A complementary output driver includes a driver input that receives an input signal which alternates between a first state and a second state. A first inverter has a first input and a first output. The first input is coupled to the driver input and the first output gene... | 09/20/2007 |
| 20070182454 | Input buffer with optimal biasing and method thereof A method and circuit of a biased input buffer is described to maximize the quality in the output signals. The input buffer includes a first stage for receiving differential input signals and generating differential internal signals as biased in response to an averaging ... | 08/09/2007 |
| 20070170953 | System and method for extending universal bus line length A system and method for recovering a high frequency component of a slew rate controlled signal propagating along a transmission line enables the high frequency component to be recovered after being lost because of slew rate control and transmission line low pass filteri... | 07/26/2007 |
| 20070164780 | Apparatus for controlling on-die termination An on-die termination control unit turns on/off a corresponding transistor according to a code signal and adjusts an on-die termination resistance so it is equal to an external resistance. An offset compensating unit detects an offset voltage from an output voltage of t... | 07/19/2007 |
| 20070132483 | Bidirectional current-mode transceiver A bidirectional current-mode transceiver is provided for improving transmission rates on a transmission line in a manner of current signal transmission, and for reducing the swing of the voltage signal on the transmission line by using a termination resistor, thus impro... | 06/14/2007 |
