Celebrity Inventors
Mark Twain (Samuel L. Clemens) received Patent No. 121,992 for "An Improvement in Adjustable and Detachable Straps for Garments." He later received two more patents: one for a self-pasting scrapbook and one for a game to help players remember important historical dates.
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| Application No. | Application Title | Issue Date |
| 20110260753 | Level Shifter with Balanced Duty Cycle A level shifter and method are provided for balancing a duty cycle of a signal. An input circuit receives a differential logic signal with two complimentary logic levels. A level transition balancing circuit balances the rise and fall times of a level shifted version of... | 10/27/2011 |
| 20110255358 | Semiconductor device having floating body type transistor A semiconductor device comprises a floating body type transistor and first and second circuits. The transistor has a floating body and a source-drain path inserted between first and second circuit nodes. The first circuit supplies a first signal to the gate of the trans... | 10/20/2011 |
| 20110133773 | High Performance Output Drivers and Anti-Reflection Circuits Long existing performance, noise, and power consumption problems of known output drivers are solved by using n-channel transistors as pull up transistors and/or p-channel transistors as pull down transistors for high performance output drivers. On-die termination-circui... | 06/09/2011 |
| 20110133772 | High Performance Low Power Output Drivers Long existing performance, noise, and power consumption problems of known output drivers are solved by using n-channel transistors as pull up transistors and/or p-channel transistors as pull down transistors for high performance output drivers. In combination with RC te... | 06/09/2011 |
| 20110043246 | DYNAMIC IMPEDANCE CONTROL FOR INPUT/OUTPUT BUFFERS A system and method of performing off chip drive (OCD) and on-die termination (ODT) are provided. A common pull-up network composed of transistors and a common pull-down network composed of transistors are employed to implement both of these functions. In drive mode, th... | 02/24/2011 |
| 20110001513 | CMOS INPUT BUFFER CIRCUIT Provided is a complementary metal oxide semiconductor (CMOS) input buffer circuit that is capable of lower voltage operation with lower current consumption. The CMOS input buffer circuit includes: a depletion type NMOS transistor including a drain connected to a power s... | 01/06/2011 |
| 20100289526 | Level shifter A level shifter includes a first level shift circuit that converts a signal level of a first pulse signal into an amplitude level of a power supply voltage, and a second level shift circuit that converts a signal level of the second pulse signal into an amplitude level.... | 11/18/2010 |
| 20100213979 | SEMICONDUCTOR DEVICE AND METHOD FOR LAYOUTING SEMICONDUCTOR DEVICE A semiconductor device is provided. The semiconductor device includes a first circuit provided between a power source voltage line and a ground line, including at least two first MOS transistors coupled in parallel and a second circuit, which is provided between the pow... | 08/26/2010 |
| 20100194432 | DEVICE FOR TRANSFORMING INPUT IN OUTPUT SIGNALS WITH DIFFERENT VOLTAGE RANGES Arrangement for accepting an input signal in a first voltage range and producing an output signal in a second voltage range. A transition detection circuit (230) detects a transition from a high level to a low level of the input signal and a control circuit (2... | 08/05/2010 |
| 20100134145 | System and Method for Converting Between CML Signal Logic Families A system includes a first CML buffer configured to receive a first bias signal and a first CML signal of a first CML logic family. The first CML buffer produces a second CML signal of the first CML logic family based on the first CML signal and the first bias signal. A ... | 06/03/2010 |
| 20100109705 | LEVEL SHIFTER A device for shifting voltage levels includes an input stage, an output stage and multiple cascode sets connected between the input stage and the output stage. The input stage includes input transistors connected to a first voltage and an input for receiving an input si... | 05/06/2010 |
| 20100085079 | Low Latency, Power-Down Safe Level Shifter In one embodiment, an apparatus comprises a circuit supplied by a first supply voltage during use, the circuit having at least a first input signal; and a level shifter supplied by the first supply voltage during use and coupled to provide the first input signal to the ... | 04/08/2010 |
| 20100073027 | LATCH STRUCTURE, FREQUENCY DIVIDER, AND METHODS FOR OPERATING SAME A latch includes three circuits. The first circuit drives a first output (QB) to a first level when a first input (D) and a first clock phase (CK) are both low, to a second level when D and CK are both high, and provides high impedance (HI-Z) when different logic levels... | 03/25/2010 |
| 20100060319 | LOW LEAKAGE AND DATA RETENTION CIRCUITRY An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coup... | 03/11/2010 |
| 20090323830 | CURRENT MODE CIRCUITRY TO MODULATE A COMMON MODE VOLTAGE In some embodiments, a chip includes transmitters to transmit differential signals on conductors; and current mode circuitry to selectively modulate a common mode voltage of the differential signals to communicate data. In other embodiments, a system includes a first ch... | 12/31/2009 |
| 20090261860 | ELECTRONIC CIRCUIT An electronic circuit is provided comprising an input (VIN) for coupling a circuit of a first voltage domain to the electronic circuit, and a first, second, third and fourth transistor coupled between a supply voltage (VDD) and a voltage (VSS). The third tran... | 10/22/2009 |
| 20090195267 | High-Voltage tolerant output driver A high-voltage tolerant output driver for use in a switching regulator is provided herein. The driver allows the switching regulator to regulate supply voltages that exceed device breakdown limits for the process technology from which the high-voltage tolerant output dr... | 08/06/2009 |
| 20090189638 | LEVEL SHIFTER CIRCUIT A level shifter comprises a voltage converting circuit, a voltage pull-up circuit, and a control signal generating circuit. The voltage converting circuit is configured to receive an input signal of a first voltage level and to output an output signal of a second voltag... | 07/30/2009 |
| 20090108870 | I/O BUFFER CIRCUIT An output buffer circuit is provided. The output buffer circuit receives a control signal (OE) and a data signal (Dout) from a first core circuit (10) and operates in a transmitting mode according to the control signal. The output buffer circuit converts the data... | 04/30/2009 |
| 20090096484 | LEVEL SHIFTERS Level shifters capable of setting logic level of the output signals thereof to a pre-defined known state during power-up are provided, in which a first logic unit is powered by a first power voltage, receives input signals with a core power voltage and comprises first a... | 04/16/2009 |
| 20090058464 | Current mode logic-complementary metal oxide semiconductor converter A current mode logic (CML)-complementary metal oxide semiconductor (CMOS) converter prevents change of a duty ratio to stably operate during an operation for converting a CML level signal into a CMOS level signal. The CML-CMOS converter includes a reference level shifti... | 03/05/2009 |
| 20090009217 | TRANSFORMATION OF AN INPUT SIGNAL INTO A LOGICAL OUTPUT VOLTAGE LEVEL WITH A HYSTERESIS BEHAVIOR It is described a circuit and a method for transforming an input signal into a logical output. The circuit (100) comprises an inverter stage (120), connected in between the first conductor (101) and the second conductor (102). The inverter st... | 01/08/2009 |
| 20090002026 | Level conversion circuit for converting voltage amplitude of signal In a level conversion circuit, two P channel MOS transistors form a current mirror circuit. When an input signal rises from the “L” level to the “H” level, an N channel MOS transistor connected to a drain of one P channel MOS transistor is brought out of conduct... | 01/01/2009 |
| 20080290901 | Voltage Shifter Circuit The present invention provides a voltage shifter circuit, in which a control circuit is used to control the pull-up circuit, so that the pull-up circuit is kept as off when the signal from the input signal source changes from a low voltage to a high voltage. Hence, the ... | 11/27/2008 |
| 20080290902 | LEVEL CONVERTER A level converter comprising an input circuit, coupled to a low power source and a first high power source, which generates a complementary first signal and second signal; and a shift circuit that outputs an output signal generated by shifting a voltage level of the inp... | 11/27/2008 |
| 20080290900 | Two-Stage Level Shifting Module For raising low voltage levels of a voltage range without over-broadening the voltage range, a first stage voltage level shifting circuit, which is capable of raising an upper bound of its input voltage range, is coupled to a second voltage level shifting circuit, which... | 11/27/2008 |
| 20080238481 | LEVEL SHIFT CIRCUIT In a level shift circuit, the threshold voltage of N-type high-voltage transistors, to whose gates the voltage of a low-voltage supply VDD is applied, is set low. An input signal IN powered by the low-voltage supply VDD is input to the gate of an N-type transistor by wa... | 10/02/2008 |
| 20080218212 | LOW TO HIGH VOLTAGE CONVERSION OUTPUT DRIVER A low to high voltage conversion output driver. The low to high voltage conversion output driver has an output coupled to a first fixed voltage via a load device and comprises a current source, a low voltage transistor, and a high voltage transistor. The current source ... | 09/11/2008 |
| 20080211541 | Precision voltage level shifter based on thin gate oxide transistors A precision voltage level shifter based on thin gate oxide transistors is disclosed. A method of a voltage level shifter includes serially connecting thin n-channel gate oxide semiconductor FETs to think n-channel gate oxide semiconductor FETs to enable the voltage leve... | 09/04/2008 |
| 20080191742 | RECEIVER CIRCUIT USING NANOTUBE-BASED SWITCHES AND TRANSISTORS Receiver circuits using nanotube-based switches and transistors. A receiver circuit includes a differential input having a first and second input link, a differential output having a first and second output link, and first and second switching elements in electrical com... | 08/14/2008 |
| 20080157816 | Level conversion circuit A level conversion circuit capable of realizing low-power/high-speed operation and suppression of variations in input/output characteristics due to variations in source voltage and temperature and device variation. The level conversion circuit comprises: a source follow... | 07/03/2008 |
| 20080157817 | METHOD AND APPARATUS FOR GENERATING A REFERENCE SIGNAL AND GENERATING A SCALED OUTPUT SIGNAL BASED ON AN INPUT SIGNAL An input signal is routed to a first logic one reference signal generator or alternatively routed to a second logic one reference signal generator based at least one a voltage level of the input signal. When the voltage level of the input signal is less than a threshold... | 07/03/2008 |
| 20080143385 | High-speed differential logic to CMOS translator architecture with low data-dependent jitter and duty cycle distortion Disclosed are various embodiments of a differential logic to CMOS logic translator including a level-shifting and buffering stage configured to receive differential inputs and to provide resulting signals with lower common mode voltage. Further, a gain stage is included... | 06/19/2008 |
| 20080143384 | PRINTED CIRCUIT UNIT BASED ON ORGANIC TRANSISTOR A printed circuit unit implementing with organic transistors is provided. The printed circuit unit includes an input signal circuit, a load circuit and a level shifter. The input signal circuit includes N serially connected organic transistors. When one of the serially ... | 06/19/2008 |
| 20080129338 | HIGH-SPEED ASYNCHRONOUS DIGITAL SIGNAL LEVEL CONVERSION CIRCUIT Provided is a high-speed asynchronous digital signal level conversion circuit converting an input signal of a first voltage level into a signal of a second voltage level. The conversion circuit is able to operate at high speed by connecting first and second nodes, at wh... | 06/05/2008 |
| 20080094105 | PROGRAMMABLE MULTIPLE SUPPLY REGIONS WITH SWITCHED PASS GATE LEVEL CONVERTERS A level conversion architecture that accommodates signals traveling between logic blocks operating at corresponding voltage levels is provided. The architecture includes pass gates connected in series between the logic blocks. One of the gates of the pass gates is suppl... | 04/24/2008 |
| 20080084231 | Method for Implementing Level Shifter Circuits and Low Power Level Shifter Circuits for Integrated Circuits A low power level shifter circuit for integrated circuits, and a design structure on which the subject circuit resides are provided. The low power level shifter circuit includes an input inverter operating in a domain of a first voltage supply. The input inverter receiv... | 04/10/2008 |
| 20080074148 | High speed level shifter Embodiments of the present invention provide level shifter circuits capable of high frequency operations. The level shifter circuit utilizes a dynamic charge injection device, which diminishes a capacitive coupling effect between a gate and a drain of input NMOS devices... | 03/27/2008 |
| 20080068043 | LOW TO HIGH VOLTAGE CONVERSION OUTPUT DRIVER A low to high voltage conversion output driver. The low to high voltage conversion output driver has an output coupled to a first fixed voltage via a load device and comprises a current source, a low voltage transistor, and a high voltage transistor. The current source ... | 03/20/2008 |
| 20080061825 | CML TO CMOS SIGNAL CONVERTER A signal regenerator is provided which includes a common mode reference generator and a signal converter circuit. A common mode reference voltage level is generated which is variable in relation to at least one of a process used to fabricate the common mode reference ge... | 03/13/2008 |
