Bizarre Patents
Smoking Cessation Lighter and Method
A lighter for tobacco products suppresses the urge to smoke by operant conditioning.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Application No. | Application Title | Issue Date |
| 20120126849 | TERMINATION CIRCUIT FOR ON-DIE TERMINATION In a semiconductor device having a terminal connected to an internal portion, a termination circuit for providing on-die termination for the terminal of the device. The termination circuit comprises a plurality of transistors, including at least one NMOS transistor and ... | 05/24/2012 |
| 20120105100 | IMPEDANCE CALIBRATION CIRCUIT AND SEMICONDUCTOR APPARATUS USING THE SAME An impedance calibration circuit includes: a first calibration unit configured to compare a first converted voltage obtained by converting a first calibration signal with a reference voltage and vary the first calibration signal; a voltage detection unit configured to a... | 05/03/2012 |
| 20120081144 | CIRCUIT AND METHOD FOR GENERATING ON-DIE TERMINATION SIGNAL AND SEMICONDUCTOR APPARATUS USING THE SAME Various embodiments of an on-die termination (ODT) signal generating circuit are disclosed. In one exemplary embodiment, the ODT signal generating circuit includes a latency unit and an ODT control signal generating unit. The latency unit is configured to receive a cloc... | 04/05/2012 |
| 20120081146 | SIGNAL LINES WITH INTERNAL AND EXTERNAL TERMINATION Embodiments of a memory controller are described. This memory controller communicates signals to a memory device via a signal line, which can be a data signal line or a command/address signal line. Termination of the signal line is divided between an external impedance ... | 04/05/2012 |
| 20120081145 | IMPEDANCE CONTROL SIGNAL GENERATION CIRCUIT AND IMPEDANCE CONTROL METHOD OF SEMICONDUCTOR CIRCUIT An impedance control signal generation circuit includes an impedance control signal generation unit configured to generate an impedance control signal in response to a command, a storage unit configured to latch and output the impedance control signal in response to an ... | 04/05/2012 |
| 20120019282 | DYNAMIC IMPEDANCE CONTROL FOR INPUT/OUTPUT BUFFERS A system and method of performing off chip drive (OCD) and on-die termination (ODT) are provided. A common pull-up network composed of transistors and a common pull-down network composed of transistors are employed to implement both of these functions. In drive mode, th... | 01/26/2012 |
| 20120013361 | Synthetic Pulse Generator for Reducing Supply Noise A source-terminated transmitter conveys digital signals over a short channel as a voltage signal that transitions between levels for each symbol transition. The transmitter produces each transition by issuing a charge pulse onto the channel, and thus creates a series of... | 01/19/2012 |
| 20120007632 | CALIBRATING RESISTANCE FOR INTEGRATED CIRCUIT An integrated circuit includes a first ODT unit and an input buffer. The first ODT unit is configured to receive at least one pull-up code and at least one pull-down code for impedance matching of a first line through which data is transferred, and adjust a resistance v... | 01/12/2012 |
| 20120007630 | IMPEDANCE CALIBRATION MODE CONTROL CIRCUIT An impedance calibration mode control circuit includes: a first signal generating unit configured to generate a first calibration control signal in response to a ZQ calibration command received after a power-up operation; and a second signal generating unit configured t... | 01/12/2012 |
| 20120007631 | INTEGRATED CIRCUIT AND METHOD FOR CONTROLLING DATA OUTPUT IMPEDANCE An integrated circuit for controlling data output impedance includes an address decoder, a selection signal decoder, and a transfer control unit. The address decoder is configured to decode an address signal and generate a selection mode signal and a first adjustment mo... | 01/12/2012 |
| 20110316580 | METHOD AND APPARATUS FOR DYNAMIC MEMORY TERMINATION Described herein are a method and an apparatus for dynamically switching between one or more finite termination impedance value settings to a memory input-output (I/O) interface of a memory in response to a termination signal level. The method comprises: setting a first... | 12/29/2011 |
| 20110316581 | SEMICONDUCTOR DEVICE WITH BUS CONNECTION CIRCUIT AND METHOD OF MAKING BUS CONNECTION A semiconductor device capable of achieving desirable communication behavior through a bus regardless of whether or not a pull-up resistor is connected on a bus line. The semiconductor device includes external pull-up determination unit and internal pull-up setting unit... | 12/29/2011 |
| 20110309857 | CIRCUITRY FOR MATCHING THE UP AND DOWN IMPEDANCES OF A VOLTAGE-MODE TRANSMITTER Some embodiments of the present invention provide a voltage-mode transmitter. The transmitter can include configuration circuitry, bias circuitry, and a set of driver slices. Each driver slice can include driver transistors which drive an output value. The outputs of ea... | 12/22/2011 |
| 20110307671 | Training a Memory Controller and a Memory Device Using Multiple Read and Write Operations Systems and methods to set a voltage value associated with a communication bus that includes memory controller coupled to a memory device are disclosed. A particular method may include performing a first calibration operation associated with first data written from a me... | 12/15/2011 |
| 20110307717 | Setting a Reference Voltage in a Memory Controller Trained to a Memory Device Systems and methods to set a voltage value associated with a memory controller coupled to a memory device are disclosed. A particular method includes comparing test data of a test path to functional data of a functional path. The functional data may be generated based o... | 12/15/2011 |
| 20110291699 | IMPEDANCE CODE GENERATION CIRCUIT, SEMICONDUCTOR DEVICE INCLUDING THE SAME, AND METHOD FOR SETTING TERMINATION IMPEDANCE An impedance code generation circuit includes a first code generation unit configured to compare a voltage of a calibration node with a reference voltage and generate a first impedance code, a code modification unit configured to generate a modified impedance code by pe... | 12/01/2011 |
| 20110291698 | IMPEDANCE ADJUSTING DEVICE An impedance adjusting device includes a calibration unit configured to generate an impedance code for adjusting a termination impedance value, a plurality of termination units configured to be enabled by resistance selection information and terminate an interface node ... | 12/01/2011 |
| 20110291700 | SEMICONDUCTOR INTEGRATED CIRCUIT A semiconductor integrated circuit includes an impedance control signal generation block configured to transmit first impedance control signals and second impedance control signals through same signal lines at predetermined time intervals, and input/output blocks config... | 12/01/2011 |
| 20110267100 | OUTPUT BUFFER CIRCUIT AND INTEGRATED CIRCUIT INCLUDING SAME An output buffer circuit includes a control unit and an output driver. The control unit generates a control signal in response to a mode signal applied from an internal circuit. The output driver selectively performs a driver operation, a termination operation or an ele... | 11/03/2011 |
| 20110267101 | CONTROLLING DYNAMIC SELECTION OF ON-DIE TERMINATION A control component outputs to an integrated circuit device an indication to apply one of a plurality of controllable termination impedance configurations at a data input of the integrated circuit device. The indication causes the integrated circuit device to apply a fi... | 11/03/2011 |
| 20110267098 | SEMICONDUCTOR DEVICE, MEMORY SYSTEM, AND METHOD FOR CONTROLLING TERMINATION OF THE SAME A semiconductor device includes a plurality of first input units configured to receive a command, a second input unit configured to receive a termination command, a termination control unit configured to be enabled by the termination command and decode the command to co... | 11/03/2011 |
| 20110267099 | Semiconductor device generating complementary output signals To include a first inverter that receives an input signal to output an inverted signal, a second inverter that receives the inverted signal to output a first internal signal, and a third inverter that receives the input signal and outputs a second internal signal by usi... | 11/03/2011 |
| 20110254584 | Switchable Passive Termination Circuits According to one exemplary embodiment, an active termination circuit includes at least one active termination branch, where the at least one active termination branch includes at least one transistor for providing an active termination output. The at least one active te... | 10/20/2011 |
| 20110248742 | Calibration circuit, semiconductor device including the same, and data processing system A method includes issuing a calibration command and performing a calibration operation in response to the calibration command. The calibration operation includes adjusting an impedance of a first replica buffer with updating a first code, the first replica buffer being ... | 10/13/2011 |
| 20110248743 | ENHANCED PERFORMANCE MEMORY SYSTEMS AND METHODS Digital memory devices and systems, including memory systems and methods for operating such memory systems are disclosed. In the embodiments, a memory system may include a processor and a memory controller communicatively coupled to the processor. A memory bus communica... | 10/13/2011 |
| 20110241727 | DYNAMIC ON-DIE TERMINATION SELECTION In an integrated circuit device having dynamically selected on-die termination, a set of data inputs are coupled respectively to a set of termination circuits, each termination circuit having multiple controllable termination impedance configurations. A termination cont... | 10/06/2011 |
| 20110242916 | ON-DIE TERMINATION CIRCUIT, DATA OUTPUT BUFFER AND SEMICONDUCTOR MEMORY DEVICE An on-die termination circuit includes a termination resistor unit connected to an external pin, and a termination control unit connected to the termination resistor unit. The termination resistor unit provides termination impedance to a transmission line connected to t... | 10/06/2011 |
| 20110241726 | ON-DIE TERMINATION CIRCUIT An on-die termination circuit includes a reference period signal generation circuit that generates a reference period signal according to a level of a reference voltage, a first period signal generation circuit that generates a first period signal according to a voltage... | 10/06/2011 |
| 20110227604 | RECEIVING CIRCUIT AND METHODS FOR CONTROLLING AND TESTING THE SAME A receiving circuit includes: a terminating resistor to set a terminating level of a transmission line for transmitting a reception signal including a signal having a first level indicating a preamble; a detection circuit to detect whether a level of the transmission li... | 09/22/2011 |
| 20110215830 | OUTPUT BUFFER CIRCUIT AND DIFFERENTIAL OUTPUT BUFFER CIRCUIT, AND TRANSMISSION METHOD An output buffer includes inverters, a delay circuit for delaying an input signal, buffers and switches. The output buffer transmits a logic signal to a transmission path and, in accordance with an amount of signal attenuation in the transmission path, creates a wavefor... | 09/08/2011 |
| 20110215831 | LOW POWER TELEMETRY SYSTEM AND METHOD A telemetry system is described in which a plurality of channels are coupled to a bus. A control subsystem controls the channels so that one of the channels presents to the bus during its designated time period a channel characteristic. The control subsystem interrogate... | 09/08/2011 |
| 20110205832 | ON-DIE TERMINATION CIRCUIT, MEMORY DEVICE, MEMORY MODULE, AND METHOD OF OPERATING AND TRAINING AN ON-DIE TERMINATION An on-die termination (ODT) circuit of a memory device comprising: a memory device having a memory core having a memory cell array; a data input/output pin connected to the memory core through a data buffer; and an on-die termination (ODT) circuit, comprising: a termina... | 08/25/2011 |
| 20110193591 | Calibration Methods and Circuits to Calibrate Drive Current and Termination Impedance Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and m... | 08/11/2011 |
| 20110193590 | SEMICONDUCTOR DEVICE AND CIRCUIT BOARD HAVING THE SEMICONDUCTOR DEVICE MOUNTED THEREON To provide a semiconductor device including a first replica buffer connected to a calibration terminal, an impedance adjusting circuit that changes an impedance of the first replica buffer according to a comparison result between a potential of the terminal and a refere... | 08/11/2011 |
| 20110187405 | TRANSCEIVER CIRCUITS A transceiver circuit supports a bidirectional mode and the bidirectional transceiver circuit is signal-compatible with JEDEC SSTL 2. A differential transceiver circuit supports a bidirectional mode and is also signal-compatible with JEDEC SSTL 2. Finally, transceiver c... | 08/04/2011 |
| 20110187406 | Semiconductor Chip And Semiconductor Module Including The Semiconductor Chip A semiconductor chip including a termination resistance and a semiconductor module including the semiconductor chip. The semiconductor chip comprising a plurality of memory cells, the semiconductor chip including: at least one first center pads disposed on a center regi... | 08/04/2011 |
| 20110169523 | ADAPTIVE TERMINATION A system for receiving data is provided. Too system includes an inductive data device, such as a device that receives high-speed data over an inductive coupling. An adjustable impedance is coupled to the inductive data device, where the adjustable impedance is used for ... | 07/14/2011 |
| 20110163778 | IMPEDANCE CALIBRATION CIRCUIT, SEMICONDUCTOR MEMORY DEVICE WITH THE IMPEDANCE CALIBRATION CIRCUIT AND LAYOUT METHOD OF INTERNAL RESISTANCE IN THE IMPEDANCE CALIBRATION CIRCUIT An impedance calibration circuit for impedance matching between a semiconductor memory device and an external device includes a driving circuit and a comparing circuit. The driving circuit has a plurality of internal resistances, with one or more of the internal resista... | 07/07/2011 |
| 20110156750 | INTEGRATED CIRCUIT DEVICE WITH DYNAMICALLY SELECTED ON-DIE TERMINATION In an integrated circuit device having dynamically selected on-die termination, a set of data inputs are coupled respectively to a set of termination circuits, each termination circuit having multiple controllable termination impedance configurations. A termination cont... | 06/30/2011 |
| 20110133772 | High Performance Low Power Output Drivers Long existing performance, noise, and power consumption problems of known output drivers are solved by using n-channel transistors as pull up transistors and/or p-channel transistors as pull down transistors for high performance output drivers. In combination with RC te... | 06/09/2011 |
