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Class 326/14 - Fail-safe


Subclass of Class 326 - Electronic digital logic circuitry
Definition: Subject matter including a device which prevents generating
No. of applications: 18
Last issue date: 12/17/2009


Application No.Application TitleIssue Date
20090309627Methodology and Apparatus for Reduction of Soft Errors in Logic Circuits
The present invention includes a circuit-level system and method for preventing the propagation of soft errors in logic cells. A radiation jammer circuit in accordance with the present invention, including an RC differentiator and a depletion mode MOS circuit, when inse...
12/17/2009
20080315911Receiver circuit
In a receiver circuit that receives data and clock signals through the cables, the number of transitions of a signal obtained based on the data or clock signal is detected by a frequency detection circuit, and when the number of transitions is not more than a predetermi...
12/25/2008
20080238472Low Power Mode Fault Recovery Method, System and Apparatus
A semiconductor integrated circuit device uses two keeper cells per configuration and/or enable bit as dual redundant storage with error detection thereof. One of the two keeper cells stores a logic level and the other keeper cell stores the inverse of that logic level ...
10/02/2008
20080197875INTEGRATED CIRCUIT
An integrated circuit is provided having at least one terminal for coupling and/or decoupling of electric signals, particularly of digital signals, and having integrated reference potential means, assigned to the terminal, for providing an electric reference potential t...
08/21/2008
20080036490Semiconductor integrated circuit device with a fail-safe IO circuit and electronic device including the same
A semiconductor IC device includes at least one IO port, a core logic, and at least one fail-safe IO circuit, the fail-safe IO circuit being coupled between the core logic and the IO port, wherein the fail-safe IO circuit is configured to receive a predetermined control...
02/14/2008
20070296455Disconnection and short detecting circuit that can detect disconnection and short of a signal line transmitting a differential clock signal
Provided is a disconnection and short detecting circuit capable of detecting disconnection and short of a signal line transmitting a differential clock signal. A differential buffer part DB1 has a first comparator to compare a non-inverting clock signal inputted ...
12/27/2007
20070262786FAULT TOLERANT ASYNCHRONOUS CIRCUITS
New and improved methods and circuit designs for asynchronous circuits that are tolerant to transient faults, for example of the type introduced through radiation or, more broadly, single—event effects. SEE-tolerant configurations are shown and described for combinati...
11/15/2007
20070205799Radiation hardened logic circuit
A radiation-hardened logic circuit prevents SET-induced transient pulses from propagating through the circuit, using two identical logic paths. The outputs of the two logic paths are fed into an exclusive-OR gate, which controls gating circuitry. The gating circuitry ca...
09/06/2007
20070201293Testing method for permanent electrical removal of an integrated circuit output
An apparatus and method of disconnecting or disabling an input/output terminal of an integrated circuit after packaging. Each input/output terminal of the integrated circuit includes a disabling device coupled thereto between the input/output terminal and the output dri...
08/30/2007
20070176627Reprogrammable field programmable gate array with integrated system for mitigating effects of single event upsets
An integrated system mitigates the effects of a single event upset (SEU) on a reprogrammable field programmable gate array (RFPGA). The system includes (i) a RFPGA having an internal configuration memory, and (ii) a memory for storing a configuration associated with the...
08/02/2007
20070115025Receiver circuit
In a receiver circuit that receives data and clock signals through the cables, the number of transitions of a signal obtained based on the data or clock signal is detected by a frequency detection circuit, and when the number of transitions is not more than a predetermi...
05/24/2007
20070103185Dual path redundancy with stacked transistor voting
A method of operation and an apparatus for radiation hardening a combinational logic circuit are presented. A section of logic that is to be radiation hardened is identified. An entire logic circuit or a portion of the logic circuit may be radiation hardened. Once the s...
05/10/2007
20070063728Logic cell with two isolated redundant outputs, and corresponding integrated circuit
The disclosure relates to a logic cell for an integrated circuit, including two redundant outputs, a first output equipped with an output transistor of type P and a second output equipped with an output transistor of type N. Such a cell includes isolation element connec...
03/22/2007
20070052442Redundancy circuits hardened against single event upsets
A decision block is incorporated into a circuit design to provide hardening against single event upset and to store data. The decision block includes a storage element that stores data as long as inputs to the decision block remain constant. The decision block receives ...
03/08/2007
20060273819Antibiotic tetrahydro-beta-carboline derivatives
Disclosed are tetrahydro-β-carboline derivatives such as structural formula I, pharmaceutical compositions comprising them and methods of treating bacterial infections. The disclosed compounds are inhibitors of PPAT (phosphopantetheine adenyl transferase), and are usef...
12/07/2006
20060145722Apparatus and method of error detection and correction in a radiation-hardened static random access memory field-programmable gate array
The present system comprises a radiation tolerant programmable logic device having logic modules and routing resources coupling together the logic modules. Configuration data lines providing configuration data control the programming of the logic modules and the routing...
07/06/2006
20060119379Single event upset hardened circuitry without sensitivity to overshoot and/or undershoot conditions
An apparatus for hardening logic circuitry against a Single-Event-Effect condition and for providing immunity to an overshoot and undershoot condition is provided. The apparatus includes undershoot-blocking and overshoot-blocking modules that are configured to be couple...
06/08/2006
20050110515FAILSAFE FOR DIFFERENTIAL CIRCUIT BASED ON CURRENT SENSE SCHEME
A system and method are described for receiving differential currents in a current mode circuit. When condition occur where the receiver inputs are floating, undriven, shorted together, or one or both shorted to ground, the output of the system remains stable. Diode con...
05/26/2005
 
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