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| Application No. | Application Title | Issue Date |
| 20100301333 | SEMICONDUCTOR DEVICE AND METHOD OF INSPECTING AN ELECTRICAL CHARACTERISTIC OF A SEMICONDUCTOR DEVICE A semiconductor device is provided with an electrode pad; and a lower layer arranged under the electrode pad. The electrode pad includes a slit section, penetrating a whole thickness of the electrode pad from a higher surface to a lower surface in contact with the lower... | 12/02/2010 |
| 20100301894 | SEMICONDUCTOR DEVICE CAPABLE OF VERIFYING RELIABILITY A semiconductor device includes an integrated semiconductor circuit unit, a chip guard-ring disposed along an outer portion of the semiconductor device, and a reliability verifying unit disposed between the integrated semiconductor circuit unit and the chip guard-ring. ... | 12/02/2010 |
| 20100301895 | Test system and test method of semiconductor integrated circuit Provided is a test system of a semiconductor integrated circuit including an output device and an input device for conducting an input/output characteristics test of the output device and the input device inside the semiconductor integrated circuit. In the system, a tra... | 12/02/2010 |
| 20100295572 | UNIVERSAL TEST SOCKET AND SEMICONDUCTOR PACKAGE TESTING APPARATUS USING THE SAME A universal test socket includes a housing frame including a side wall, an inner protruding portion protruding inwardly from the side wall, and a through window formed at a center portion of the housing frame, wherein the through window is surrounded by the side wall, a... | 11/25/2010 |
| 20100289517 | BUILT OFF TESTING APPARATUS A built off testing apparatus coupled between a semiconductor device and an external testing apparatus to test a semiconductor device. The built off testing apparatus can include a frequency multiplying unit to generate a test clock frequency by multiplying the frequenc... | 11/18/2010 |
| 20100283499 | NON-CONTACT TESTING OF PRINTED ELECTRONICS Apparatus and methods for non-contact testing of electronic components printed on a substrate (3) are provided. Test circuits (11) are printed on the substrate (3) at the same time as the desired electronic component. The test circuits (11) a... | 11/11/2010 |
| 20100277196 | SEMICONDUCTOR TEST SYSTEM AND METHOD A method of testing semiconductor devices, the method includes the steps of making a first set of electrical connections to a first set of devices to allow a first set of tests to be performed on that set of devices and concurrently making a second set of electrical con... | 11/04/2010 |
| 20100271065 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MEASURING SYSTEM A semiconductor device includes: a well of a second conductive type formed on or above a semiconductor substrate of a first conductive type; a first diffusion layer of the second conductive type formed in a surface portion of the well; a second diffusion layer of the fi... | 10/28/2010 |
| 20100264951 | INTERCONNECTION CARD FOR INSPECTION, MANUFACTURE METHOD FOR INTERCONNECTION CARD, AND INSPECTION METHOD USING INTERCONNECTION CARD Recesses are formed on one surface of a substrate. A conductive film covers an inner surface of each of the recesses. This conductive film contacts a bump of a semiconductor device to be inspected and is electrically connected to the bump. It is therefore possible to pr... | 10/21/2010 |
| 20100264204 | Fingerprinted circuits and methods of making and indenifying same A circuit having a fingerprint for identification of a particular instantiation of the circuit. The circuit comprises a plurality of digital circuits or gates, the plurality digital circuits or gates each having an analog input and wherein each of the digital circuits o... | 10/21/2010 |
| 20100259287 | SEMICONDUCTOR TEST EQUIPMENT A test head (3) has test electrodes (5) for electrical connection between a test unit (4) and interface board terminals (6). The state of electrical connection of the test electrodes (5) to the interface board terminals (6) is a... | 10/14/2010 |
| 20100259291 | DEVICE FOR CHARACTERIZING THE ELECTRO-OPTICAL PERFORMANCE OF A SEMICONDUCTOR COMPONENT A device for characterizing the electro-optical performance of a semiconductor component includes a chamber containing a controlled atmosphere; a measuring head equipped with conductive probes for contacting the electrical interfaces of said component and connected to a... | 10/14/2010 |
| 20100259292 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND TEST METHOD THEREFOR A semiconductor integrated circuit device includes: a normal output signal counter that counts number of times a normal output signal is output by the circuit under test in response to a preset one of the input signals of the input signal set, in case where a circuit un... | 10/14/2010 |
| 20100253381 | On-Chip Logic To Support In-Field Or Post-Tape-Out X-Masking In BIST Designs Techniques for masking unknown and irrelevant response values that may be produced by a BIST process. Masking circuitry is provided for selectively masking the response values obtained from a BIST process. The operation of the selective masking circuitry is controlled b... | 10/07/2010 |
| 20100253374 | Method and apparatus for Terminating A Test Signal Applied To Multiple Semiconductor Loads Under Test Apparatus for terminating a test signal applied to multiple semiconductor loads under test is described—for example apparatus for interfacing a test signal between a tester and a semiconductor device under test (DUT). In some examples, a probe card assembly may includ... | 10/07/2010 |
| 20100244883 | COMPENSATION FOR VOLTAGE DROP IN AUTOMATIC TEST EQUIPMENT Providing reliable testing of a device under test (DUT) by compensating for a reduced voltage inside the device without changing the internal circuitry of the device. The DUT has multiple connection terminals for connecting to the test equipment including at least first... | 09/30/2010 |
| 20100244870 | DOPANT PROFILE MEASUREMENT MODULE, METHOD AND APPARATUS An apparatus comprises: a first signal source; a dopant profile measurement module (DPPM) configured to receive a portion of the signal from the signal source; a probe tip connected to the reflective coupler; a load connected in parallel with the probe tip; and a second... | 09/30/2010 |
| 20100244882 | Burn-In Test Method and System A method for performing a burn-in test of a metal wire for a signal transmission of a semiconductor device including driving a first terminal of the metal wire with a first voltage and forming a current path in the metal wire by driving a second terminal of the metal wi... | 09/30/2010 |
| 20100244880 | TEST APPARATUS AND DRIVER CIRCUIT Provided is a test apparatus that tests a device under test, comprising a driver circuit that generates an output signal according to a prescribed input pattern, and supplies the output signal to the device under test; and a measuring section that measures a response si... | 09/30/2010 |
| 20100244881 | TRANSMISSION CHARACTERISTICS MEASUREMENT APPARATUS, TRANSMISSION CHARACTERISTICS MEASUREMENT METHOD, AND ELECTRONIC DEVICE Provided is a transfer characteristic measurement apparatus that measures a transfer characteristic of a circuit under test between input and output, comprising a test signal input section that generates a test signal by adding together a carrier signal having a prescri... | 09/30/2010 |
| 20100237894 | METHOD TO DETERMINE NEEDLE MARK AND PROGRAM THEREFOR Disclosed is a method to determine a needle mark, which can more accurately determine whether marks formed on electrode pads of devices are probe needle marks, thereby significantly reducing misdetermination of the marks as the probe needle marks. The method includes gi... | 09/23/2010 |
| 20100237893 | SEMICONDUCTOR TEST APPARATUS AND TEST METHOD FOR SEMICONDUCTOR DEVICE A semiconductor test apparatus comprising: a contact-resistance calculating unit that calculates contact resistance of a measuring jig using power supply current and internal voltage obtained when power supply voltage is applied; a regression-expression calculating unit... | 09/23/2010 |
| 20100231254 | METHOD FOR CONFIGURING COMBINATIONAL SWITCHING MATRIX AND TESTING SYSTEM FOR SEMICONDUCTOR DEVICES USING THE SAME A method for configuring a combinational switching matrix comprises the steps of setting a first switching module and a second switching module, coupling at least one of the output ports of the first switching module with at least one of the input ports of the second sw... | 09/16/2010 |
| 20100231248 | SOCKET, AND TEST APPARATUS AND METHOD USING THE SOCKET An apparatus for testing electric characteristics of a test object including first connection terminals on a bottom surface and second connection terminals on a top surface, the apparatus comprises a test board comprising first pads on a predetermined surface; a socket ... | 09/16/2010 |
| 20100231253 | METHOD AND APPARATUS FOR INSPECTING SEMICONDUCTOR DEVICE The magnitude of an amplitude waveform of an electromagnetic wave generated when irradiating a pulse laser beam to a structure A including diffusion regions provided in the structure of a semiconductor device to be inspected is compared with the magnitude of an amplitud... | 09/16/2010 |
| 20100231252 | TESTABLE INTEGRATED CIRCUIT AND IC TEST METHOD An integrated circuit (200) comprises a functional block (130) conductively coupled to a supply rail (110) via one or more switches (115). The IC further comprises selection means (220) responsive to a test enable signal for activating... | 09/16/2010 |
| 20100225343 | Probe card, semiconductor testing device including the same, and fuse checking method for probe card A probe card according to an exemplary aspect of the present invention includes: a force terminal supplied with a first power supply voltage; a probe needle that supplies a voltage corresponding to the first power supply voltage to a semiconductor integrated circuit to ... | 09/09/2010 |
| 20100225346 | DEVICE AND METHOD FOR EVALUATING ELECTROSTATIC DISCHARGE PROTECTION CAPABILITIES A device and a method for evaluating ESD protection capabilities of an integrated circuit, the method includes: connecting multiple test probe to multiple integrated circuit testing points. The method is characterized by repeating the stages of: (i) charging a discharge... | 09/09/2010 |
| 20100225347 | Circuit for Measuring Magnitude of Electrostatic Discharge (ESD) Events for Semiconductor Chip Bonding A circuit for recording a magnitude of an ESD event during semiconductor assembly includes a voltage divider connected between an input and a ground. The circuit also includes a measurement block having a recorder device. Each measurement block receives current from a s... | 09/09/2010 |
| 20100225348 | METHOD AND APPARATUS FOR STATISTICAL CMOS DEVICE CHARACTERIZATION A unified test structure having a large number of electronic devices under test is used to characterize both capacitance-voltage parameters (C-V) and current-voltage parameters (I-V) of the devices. The devices are arranged in an array of columns and rows, and selected ... | 09/09/2010 |
| 20100213963 | SEMICONDUCTOR INTEGRATED CIRCUIT TEST METHOD A wafer of semiconductor integrated circuits with wafer-level chip-scale packages is tested in two stages. The chip-scale packages include conductive posts extending through a sealing layer and capped by terminals. Measurements strongly affected by contact resistance ar... | 08/26/2010 |
| 20100213966 | Comparator with latching function A comparison amplification unit compares a level of a signal in a positive line with that of a signal in a negative line and latches a comparison result. An input terminal of a first inverter is connected to the positive line and an output terminal thereof is connected ... | 08/26/2010 |
| 20100213968 | TESTING INTEGRATED CIRCUITS A test insert for an integrated circuit according to the present invention comprises access contacts and an electrical path. Furthermore, there may be additional access contacts and a plurality of different electrical paths. The electrical path is comprised of a plurali... | 08/26/2010 |
| 20100213967 | TEST APPARATUS A test apparatus is configured such that two adjacent channels form a pair. Timing comparators determine the level of first output data fed from a DUT, respectively, timed in accordance with strobe signals, respectively. Clock envelope extractors extract envelopes of a ... | 08/26/2010 |
| 20100213965 | METHOD AND APPARATUS OF TESTING DIE TO DIE INTERCONNECTION FOR SYSTEM IN PACKAGE Method and apparatus of testing die to die interconnection for system in package (SiP). For testing a die to die interconnection connected between two pads of two dice, an IO buffer, e.g., a bi-directional IO buffer, in one of the two dice coupled to one of the two pads... | 08/26/2010 |
| 20100206768 | DEVICE AND METHOD FOR ALIGNING AND HOLDING A PLURALITY OF SINGULATED SEMICONDUCTOR COMPONENTS IN RECEIVING POCKETS OF A TERMINAL CARRIER In a device and a method for aligning and holding a plurality of singulated semi-conductor components in receiving pockets of a terminal carrier (5) that are separated from each other, the terminal carrier (5) has spring elements (12a, 12<... | 08/19/2010 |
| 20100207653 | Apparatus for testing semiconductor device An apparatus for testing an electrical property of a semiconductor device includes a substrate support unit, a tester head above the substrate support unit, the tester head including a base, a probe card connected to the base of the tester head, and a temperature contro... | 08/19/2010 |
| 20100207655 | Method and Apparatus for Small Die Low Power System-on-chip Design with Intelligent Power Supply Chip A method and system of system-on-chip design that provides the benefits of reduced design time, a smaller die size, lower power consumption, and reduced costs in chip design and production. The process seeks to remove the worst performance and worst power case scenarios... | 08/19/2010 |
| 20100201395 | Semiconductor device and defect analysis method for semiconductor device A semiconductor device and a defect analysis method of a semiconductor device, in which a failure location can be easily identified. The semiconductor device is provided with at least 2N resistor patterns having a fixed form, and being divided into N groups; 08/12/2010 | |
| 20100201392 | Semiconductor test system with self-inspection of electrical channel for Pogo tower A semiconductor test system with self-inspection of an electrical channel for a Pogo tower is disclosed, which provides a short board and closed loops are formed respectively by providing various kinds of contacts to correspondingly electrically contact various kinds of... | 08/12/2010 |
