Bizarre Patents
An enclosure for small animals which is wearable on the front or back of an animate being.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Application No. | Application Title | Issue Date |
| 20130126955 | Methods and Apparatus for Hybrid MOS Capacitors in Replacement Gate Process Methods and apparatus for hybrid MOS capacitors in replacement gate process. A method is disclosed including patterning a gate dielectric layer and a polysilicon gate layer to form a polysilicon gate region over a substrate; forming an inter-level dielectric layer over ... | 05/23/2013 |
| 20130126953 | Methods and Apparatus for MOS Capacitors in Replacement Gate Process Methods and apparatus for polysilicon MOS capacitors in a replacement gate process. A method includes disposing a gate dielectric layer over a semiconductor substrate; disposing a polysilicon gate layer over the dielectric layer; patterning the gate dielectric layer and... | 05/23/2013 |
| 20130119449 | SEMICONDUCTOR DEVICE WITH SEAL RING WITH EMBEDDED DECOUPLING CAPACITOR A seal ring for semiconductor devices is provided with embedded decoupling capacitors. The seal ring peripherally surrounds an integrated circuit chip in a seal ring area. The at least one embedded decoupling capacitor may include MOS capacitors, varactors, MOM capacito... | 05/16/2013 |
| 20130107630 | NON-VOLATILE MEMORY DEVICES HAVING VERTICAL DRAIN TO GATE CAPACITIVE COUPLING Vertically fabricated non-volatile memory devices having capacitive coupling between a drain region and a floating gate. A two terminal programmable non-volatile device includes a floating gate disposed vertically about a substrate, wherein the floating gate comprises a... | 05/02/2013 |
| 20130092993 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE A semiconductor device includes a substrate, an interlayer insulation layer, first transistors, a multilayered interconnect layer, capacitance devices, metal interconnects, and first contacts. Interlayer insulation films are disposed over the substrate. The first transi... | 04/18/2013 |
| 20130075801 | SELF-ADJUSTED CAPACITIVE STRUCTURE A method for producing a capacitive structure in a semiconductor body includes forming a first trench in a first surface of the semiconductor body, forming a first dielectric layer on sidewalls and the bottom of the first trench, forming a first electrode layer on the f... | 03/28/2013 |
| 20130076335 | INTEGRATED CIRCUIT INCLUDING A VOLTAGE DIVIDER AND METHODS OF OPERATING THE SAME An integrated circuit includes at least one FLASH memory array and at least one capacitor array disposed over a substrate. The at least one capacitor array includes a plurality of capacitor cell structures. The capacitor cell structures each includes a first capacitor e... | 03/28/2013 |
| 20130056813 | CAPACITOR STRUCTURE APPLIED TO INTEGRATED CIRCUIT A capacitor structure applied to an integrated circuit (IC) is provided. The capacitor structure includes a metal-oxide semiconductor (MOS) capacitor and two metal structures with different structures. The MOS capacitor has a first terminal and a second terminal. The tw... | 03/07/2013 |
| 20130056763 | SEMICONDUCTOR DEVICE An object is to provide a semiconductor device that can realize a function of a thyristor without complication of the process. A semiconductor device including a memory circuit that stores a predetermined potential by reset operation and initialization operation is prov... | 03/07/2013 |
| 20130043562 | Compressive Polycrystalline Silicon Film and Method of Manufacture Thereof In one embodiment a method of forming a compressive polycrystalline semiconductive material layer is disclosed. The method comprises forming a polycrystalline semiconductive seed layer over a substrate and forming a silicon layer by depositing silicon directly on the po... | 02/21/2013 |
| 20130026549 | SEMICONDUCTOR INTEGRATED CIRCUIT HAVING CAPACITOR FOR PROVIDING STABLE POWER AND METHOD OF MANUFACTURING THE SAME A capacitor and a method of manufacturing the same are provided. A dummy capacitor group is formed in the peripheral circuit area and includes a dummy storage node contact unit, a dielectric, and a dummy plate electrode. A metal oxide semiconductor (MOS) capacitor is fo... | 01/31/2013 |
| 20130026551 | SEMICONDUCTOR INTEGRATED CIRCUIT HAVING RESERVOIR CAPACITOR A semiconductor integrated circuit including a large capacity reservoir capacitor to provide suitable power is provided. The semiconductor integrated circuit includes a semiconductor substrate in which a cell area and a peripheral circuit area are defined, a MOS capacit... | 01/31/2013 |
| 20130015514 | SINGLE POLY NON-VOLATILE MEMORY CELLS A non-volatile memory cell that includes a semiconductor substrate; a coupling capacitor located in a first active region of the semiconductor substrate; and at a shared second active region of the semiconductor substrate, a sense transistor and a tunnelling capacitor c... | 01/17/2013 |
| 20120306567 | ADJUSTABLE CAPACITANCE STRUCTURE A capacitance structure comprises a plurality of metal oxide silicon (MOS) capacitors. A first end of each MOS capacitor of the plurality of MOS capacitors is coupled together at an effective node. A second end of each MOS capacitor of the plurality of MOS capacitors is... | 12/06/2012 |
| 20120293202 | PROGRAMMABLE LOGIC DEVICE An object is to provide a programmable logic device which can hold configuration data even when a power supply potential is not supplied, has short start-up time of a logic block after the power is supplied, and can operate with low power. A transistor in a memory porti... | 11/22/2012 |
| 20120292678 | BI-DIRECTIONAL SELF-ALIGNED FET CAPACITOR A method of forming a field effect transistor (FET) capacitor includes forming a channel region; forming a gate stack over the channel region; forming a first extension region on a first side of the gate stack, the first extension region being formed by implanting a fir... | 11/22/2012 |
| 20120292679 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF A memory cell of a nonvolatile memory and a capacitive element are formed over the same semiconductor substrate. The memory cell includes a control gate electrode formed over the semiconductor substrate via a first insulating film, a memory gate electrode formed adjacen... | 11/22/2012 |
| 20120286341 | Adding Decoupling Function for TAP Cells A tap cell includes a well region and a well pickup region on the well region; a VDD power rail; and a VSS power rail. A MOS capacitor includes a gate electrode line acting as a first capacitor plate, and the well pickup region acting as a part of a second capacitor pla... | 11/15/2012 |
| 20120273858 | SEMICONDUCTOR MEMORY DEVICE An object is to provide a semiconductor memory device that enables low power consumption of a memory cell of a CAM including a nonvolatile memory device. Another object is to provide a semiconductor memory device without degradation due to repeated data writing. Still a... | 11/01/2012 |
| 20120273861 | METHOD OF DEPOSITING GATE DIELECTRIC, METHOD OF PREPARING MIS CAPACITOR, AND MIS CAPACITOR The present invention relates to a method of depositing a gate dielectric, a method of preparing a MIS capacitor and the MIS capacitor. In the method of depositing the gate dielectric, a semiconductor substrate surface is preprocessed with oxygen plasma and nitrogen-con... | 11/01/2012 |
| 20120248518 | ISOLATION STRUCTURE AND DEVICE STRUCTURE INCLUDING THE SAME An isolation structure is described, including a doped semiconductor layer disposed in a trench in a semiconductor substrate and having the same conductivity type as the substrate, gate dielectric between the doped semiconductor layer and the substrate, and a diffusion ... | 10/04/2012 |
| 20120211814 | TRENCH STRUCTURE AND METHOD OF FORMING THE TRENCH STRUCTURE Disclosed are embodiments of an improved deep trench capacitor structure and memory device that incorporates this deep trench capacitor structure. The deep trench capacitor and memory device embodiments are formed on a semiconductor-on-insulator (SOI) wafer such that th... | 08/23/2012 |
| 20120211812 | HIGH-SPEED HIGH-POWER SEMICONDUCTOR DEVICES High-speed high-power semiconductor devices are disclosed. In an exemplary design, a high-speed high-power semiconductor device includes a source, a drain to provide an output signal, and an active gate to receive an input signal. The semiconductor device further includ... | 08/23/2012 |
| 20120193758 | SEMICONDUCTOR APPARATUS AND MANUFACTURING METHOD THEREOF A semiconductor apparatus includes a first capacitor formed in a normal cell area and including a lower electrode coupled to one end of a cell transistor, and a second capacitor formed in a dummy cell area and including a lower electrode coupled to a power terminal.... | 08/02/2012 |
| 20120193632 | SILICON STRUCTURE AND MANUFACTURING METHODS THEREOF AND OF CAPACITOR INCLUDING SILICON STRUCTURE Provided is a silicon structure with a three-dimensionally complex shape. Further provided is a simple and easy method for manufacturing the silicon structure with the use of a phenomenon in which an ordered pattern is formed spontaneously to form a nano-structure. Plas... | 08/02/2012 |
| 20120161220 | SEMICONDUCTOR DEVICE The degree of integration of a semiconductor device is enhanced and the storage capacity per unit area is increased. The semiconductor device includes a first transistor provided in a semiconductor substrate and a second transistor provided over the first transistor. In... | 06/28/2012 |
| 20120132971 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME A semiconductor device includes a semiconductor substrate having a first gate groove having first and second side walls facing to each other. A first gate insulating film covers the first and second side walls. A first gate electrode is disposed on the first gate insula... | 05/31/2012 |
| 20120112282 | Germanium Field Effect Transistors and Fabrication Thereof Germanium field effect transistors and methods of fabricating them are described. In one embodiment, the method includes forming a germanium oxide layer over a substrate and forming a metal oxide layer over the germanium oxide layer. The germanium oxide layer and the me... | 05/10/2012 |
| 20120087191 | Symmetric, Differential Nonvolatile Memory Cell Some embodiments relate to a differential memory cell. The memory cell includes a first transistor having a source, a drain, a gate, and a body. A first capacitor has a first plate and a second plate, wherein the first plate is coupled to the gate of the first transisto... | 04/12/2012 |
| 20120068238 | LOW IMPEDANCE TRANSMISSON LINE Transmission lines employing transmission line units or elements within integrated circuits (ICs) are well-known. Typically, different heights for these transmission line units can vary the characteristics of the cell (and transmission line), and there is typically a tr... | 03/22/2012 |
| 20120061739 | METHOD FOR FABRICATING CAPACITOR AND SEMICONDUCTOR DEVICE USING THE SAME Provided are a method for fabricating a capacitor and a semiconductor device using the same. The semiconductor device includes a MOS transistor capacitor, first and second plate capacitors, and a metal interconnection. The MOS transistor capacitor is arranged between a ... | 03/15/2012 |
| 20120056256 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME A semiconductor device includes a first semiconductor pillar, a second semiconductor pillar, and a first wiring. The first semiconductor pillar includes a first diffusion region. The second semiconductor pillar is adjacent to the first semiconductor pillar. The first wi... | 03/08/2012 |
| 20120049263 | SEMICONDUCTOR DEVICE HAVING EXTRA CAPACITOR STRUCTURE AND MANUFACTURING METHOD THEREOF A semiconductor device includes a semiconductor substrate having a conductive type, a source metal layer, a gate metal layer, at least one transistor device, a heavily doped region having the conductive type, a capacitor dielectric layer, a conductive layer. The source ... | 03/01/2012 |
| 20120049261 | SEMICONDUCTOR DEVICE In a semiconductor device of the invention, a semiconductor pillar configuring a vertical MOS transistor has an upper pillar having a first width and a lower pillar having a second width. A side surface of the upper pillar is covered with a second insulation film and a ... | 03/01/2012 |
| 20120043595 | CAPACITOR DEVICE AND METHOD OF FABRICATING THE SAME A capacitor device includes a substrate including a first well having a first conductivity type and a first voltage applied thereto and a second well having a second conductivity type and a second voltage applied thereto; and a gate electrode disposed on an upper portio... | 02/23/2012 |
| 20120044028 | ADAPTIVE ON DIE DECOUPLING DEVICES AND METHODS Semiconductor dies and methods are described, such as those including a first capacitive pathway having a first effective series resistance (ESR) and a second capacitive pathway having an adjustable ESR. One such device provides for optimizing the semiconductor die for ... | 02/23/2012 |
| 20120039131 | LOW-VOLTAGE EEPROM ARRAY A low-voltage EEPROM array, which has a plurality of parallel bit lines, parallel word lines and parallel common source lines is disclosed. The bit lines include a first bit line. The word lines include a first word line and a second word line. The common source lines i... | 02/16/2012 |
| 20120037971 | NONVOLATILE MEMORY DEVICE AND METHOD OF FORMING THE SAME A nonvolatile memory device has a first active region and a second active region defined in a substrate by a device isolation layer, a Metal Oxide Silicon Field-Effect Transistor (MOSFET) disposed on the first active region and including a first electrode pattern, and a... | 02/16/2012 |
| 20120032244 | Compact Semiconductor Package with Integrated Bypass Capacitor A top-side cooled compact semiconductor package with integrated bypass capacitor is disclosed. The top-side cooled compact semiconductor package includes a circuit substrate with terminal leads, numerous semiconductor dies bonded atop the circuit substrate, numerous ele... | 02/09/2012 |
| 20120032279 | III-V METAL-OXIDE-SEMICONDUCTOR DEVICE A barrier layer, hafnium oxide layer, between a III-V semiconductor layer and an lanthanum oxide layer is used to prevent interaction between the III-V semiconductor layer and the lanthanum oxide layer. Meanwhile, the high dielectric constant of the lanthanum oxide can ... | 02/09/2012 |
