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| Application No. | Application Title | Issue Date |
| 20120126321 | SEMICONDUCTOR DEVICE AND METHOD OF MAKING THE SAME A substrate having semiconductor material and a surface that supports a gate electrode and defines a surface normal direction is provided. The substrate can include a drift region including a first dopant type. A well region can be disposed adjacent to the drift region ... | 05/24/2012 |
| 20120126295 | BORDERLESS CONTACT FOR REPLACEMENT GATE EMPLOYING SELECTIVE DEPOSITION A self-aligned gate cap dielectric can be employed to form a self-aligned contact to a diffusion region, while preventing electrical short with a gate conductor due to overlay variations. In one embodiment, an electroplatable or electrolessly platable metal is selective... | 05/24/2012 |
| 20120126329 | FINFET PROCESS COMPATIBLE NATIVE TRANSISTOR Provided is a top-channel only finFET device. The devices described herein may provide a native device that is compatible with a finFET process flow. A gate may be formed on the top of a fin providing the channel region of the device. In an embodiment, the gate is provi... | 05/24/2012 |
| 20120126341 | USING LOW PRESSURE EPI TO ENABLE LOW RDSON FET A method for forming an epitaxial layer on a substrate may have the steps of: forming a heavily doped silicon substrate; depositing an epitaxial layer at sub atmospheric pressure on the heavily doped silicon substrate; and implanting dopant into the epitaxial layer by i... | 05/24/2012 |
| 20120126334 | BREAKDOWN VOLTAGE IMPROVEMENT WITH A FLOATING SUBSTRATE The present disclosure provides a semiconductor device that includes a substrate having a resistor element region and a transistor region, a floating substrate in the resistor element region of the substrate, an epitaxial layer disposed over the floating substrate, and ... | 05/24/2012 |
| 20120126226 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME, AND ELECTRIC DEVICE It is an object of the present invention to simplify steps needed to process a wiring in forming a multilayer wiring. In addition, when a droplet discharging technique or a nanoimprint technique is used to form a wiring in a contact hole having a comparatively long diam... | 05/24/2012 |
| 20120126289 | METHOD OF FORMING A SEMICONDUCTOR STRUCTURE A method of forming a semiconductor structure comprises forming a first layer of silicon and then forming a second, silicon germanium, layer adjacent the silicon layer. A thin third layer of silicon is then formed adjacent the second layer. A gate structure is then form... | 05/24/2012 |
| 20120126343 | Self Aligned Silicided Contacts Structures and methods of forming self aligned silicided contacts are disclosed. The structure includes a gate electrode disposed over an active area, a liner disposed over the gate electrode and at least a portion of the active area, an insulating layer disposed over t... | 05/24/2012 |
| 20120126883 | VERTICALLY STACKED FIN TRANSISTORS AND METHODS OF FABRICATING AND OPERATING THE SAME A semiconductor device is disclosed having vertically stacked (also referred to as vertically offset) transistors in a semiconductor fin. The semiconductor fin may include lower transistors separated by a first trench and having a source and drain in a first doped regio... | 05/24/2012 |
| 20120104513 | FIELD EFFECT TRANSISTOR HAVING AN ASYMMETRIC GATE ELECTRODE The gate electrode of a metal oxide semiconductor field effect transistor (MOSFET) comprises a source side gate electrode and a drain side gate electrode that abut each other near the middle of the channel. In one embodiment, the source side gate electrode comprises a s... | 05/03/2012 |
| 20120104504 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME Provided are a semiconductor device and a fabricating method thereof. The semiconductor device includes a substrate having a trench that defines an active region, an isolation layer that buries the trench, a pro-oxidant region formed at an upper corner portion of the tr... | 05/03/2012 |
| 20120104497 | HIGH VOLTAGE DRAIN EXTENSION ON THIN BURIED OXIDE SOI An integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel) so that the drain or body region is coupled to the handle wafer through a p-n junction. An integrated c... | 05/03/2012 |
| 20120104476 | ELECTRONIC DEVICE WITH ASYMMETRIC GATE STRAIN The use of strained gate electrodes in integrated circuits results in a transistor having improved carrier mobility, improved drive characteristics, and reduced source drain junction leakage. The gate electrode strain can be obtained through non symmetric placement of s... | 05/03/2012 |
| 20120104514 | Semiconductor Devices and Methods of Manufacturing the Same Provided are a semiconductor device, which can facilitate a salicide process and can prevent a gate from being damaged due to misalign, and a method of manufacturing of the semiconductor device. The method includes forming a first insulation layer pattern on a substrate... | 05/03/2012 |
| 20120104469 | REPLACEMENT GATE MOSFET WITH A HIGH PERFORMANCE GATE ELECTRODE In a replacement gate scheme, a continuous material layer is deposited on a bottom surface and a sidewall surface in a gate cavity. A vertical portion of the continuous material layer is removed to form a gate component of which a vertical portion does not extend to a t... | 05/03/2012 |
| 20120104515 | TRANSISTORS AND SEMICONDUCTOR DEVICES WITH OXYGEN-DIFFUSION BARRIER LAYERS Embodiments of transistors comprise a gate stack overlying a semiconductor material. The gate stack comprises a deposited oxide layer overlying the semiconductor material, an oxygen-diffusion barrier layer overlying the deposited oxide layer, a high-k dielectric layer o... | 05/03/2012 |
| 20120104516 | METAL SILICIDE FORMATION Techniques for forming metal silicide contact pads on semiconductor devices are disclosed, and in one exemplary embodiment, a method may comprise depositing a metal layer on and between a plurality of raised silicon-based features formed on a semiconductor substrate, th... | 05/03/2012 |
| 20120104502 | METHOD OF PRODUCING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE Disclosed is a method of producing a semiconductor device, able to form a source/drain of a Schottky junction (FET) with simple steps and able to improve the device characteristics. A gate is formed on an element region defined in a silicon substrate layer by element is... | 05/03/2012 |
| 20120104477 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF A semiconductor device fabrication method includes the steps of (a) forming a dielectric film on a semiconductor substrate; (b) etching the dielectric film by a dry process; and (c) supplying thermally decomposed atomic hydrogen onto the semiconductor substrate under a ... | 05/03/2012 |
| 20120104473 | TRANSISTOR AND METHOD FOR FORMING THE SAME The present invention relates to a transistor and the method for forming the same. The transistor of the present invention comprises a semiconductor substrate; a gate dielectric layer formed on the semiconductor substrate; a gate formed on the gate dielectric layer; a c... | 05/03/2012 |
| 20120104472 | FIN-LIKE FIELD EFFECT TRANSISTOR (FINFET) DEVICE AND METHOD OF MANUFACTURING SAME A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary method includes providing a semiconductor substrate; forming a first fin structure and a second fin structure over the semiconductor substrate; forming a gate structure over a portion ... | 05/03/2012 |
| 20120104471 | CONTACT STRUCTURE FOR REDUCING GATE RESISTANCE AND METHOD OF MAKING THE SAME A semiconductor device having a gate on a substrate with source/drain (S/D) regions adjacent to the gate. A first dielectric layer overlays the gate and the S/D regions, the first dielectric layer having first contact holes over the S/D regions with first contact plugs ... | 05/03/2012 |
| 20120104486 | TRANSISTOR AND METHOD FOR FORMING THE SAME The present invention relates to a transistor and the method for forming the same. The transistor of the present invention comprises a semiconductor substrate; a gate dielectric layer formed on the semiconductor substrate; a gate formed on the gate dielectric layer; and... | 05/03/2012 |
| 20120104475 | FIELD EFFECT TRANSISTORS (FETS) AND METHODS OF MANUFACTURE An improved field effect transistors (FETs) and methods of manufacturing the field effect transistors (FETs) are provided. The method of manufacturing a zero capacitance random access memory cell (ZRAM) includes comprises forming a finFET on a substrate and enhancing a ... | 05/03/2012 |
| 20120080756 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME A semiconductor device includes a high dielectric gate insulating film formed on a substrate, and a metal gate electrode formed on the high dielectric gate insulating film. The metal gate electrode includes a crystalline portion and an amorphous portion. A halogen eleme... | 04/05/2012 |
| 20120080760 | Dielectric structure, transistor and manufacturing method thereof The present invention discloses a dielectric structure, a transistor and a manufacturing method thereof with praseodymium oxide. The transistor with praseodymium oxide comprises at least a III-V substrate, a gate dielectric layer and a gate. The gate dielectric layer is... | 04/05/2012 |
| 20120080746 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF Disclosed herein is a fabrication method of a semiconductor device to order to increase an operation liability of the semiconductor device. A method for fabricating a semiconductor device comprises forming a recess in a semiconductor substrate, forming a word line in a ... | 04/05/2012 |
| 20120080777 | TRIPLE OXIDATION ON DSB SUBSTRATE According to certain embodiments, a semiconductor structure is formed having a gate oxide formed over a semiconductor substrate. The gate oxide is formed as to have three different regions characterized by a different average thickness of gate oxide in each region. A fi... | 04/05/2012 |
| 20120080723 | FABRICATING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE FABRICATED USING THE SAME METHOD A fabricating method of a semiconductor device includes providing a substrate having a first region and a second region, forming a plurality of first gates in the first region of the substrate, such that the first gates are spaced apart from each other at a first pitch,... | 04/05/2012 |
| 20120080748 | TRENCH MOSFET WITH SUPER PINCH-OFF REGIONS A trench MOSFET with short channel length and super pinch-off regions is disclosed, wherein the super pinch-off regions are implemented by forming at least two type pinch-off regions for punch-through prevention: a first type pinch-off region with a wide mesa width gene... | 04/05/2012 |
| 20120080729 | FIELD EFFECT TRANSISTOR A lateral field-effect transistor capable of improving switching speed and reducing operationally defective products is provided. A gate wiring has a base, a plurality of fingers protruding from the base, and a connection connecting tips of adjacent fingers. The finger ... | 04/05/2012 |
| 20120081941 | SEMICONDUCTOR MEMORY DEVICE HAVING AN ELECTRICALLY FLOATING BODY TRANSISTOR A semiconductor memory cell is formed in a semiconductor. The semiconductor memory cell includes: a floating body region defining at least a portion of a surface of the semiconductor memory cell, the floating body region having a first conductivity type; and a buried re... | 04/05/2012 |
| 20120080736 | SEMICONDUCTOR DEVICE An antifuse whose internal written information cannot be analyzed even by utilizing methods to determine whether there is a charge-up in the electrodes. The antifuse includes a gate insulation film, a gate electrode, and a first diffusion layer. A second diffusion layer... | 04/05/2012 |
| 20120068241 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME According to one embodiment, a memory device includes first and second fin type stacked structures each includes first to i-th memory strings (i is a natural number except 1) that are stacked in a first direction, the first and second fin type stacked structures which e... | 03/22/2012 |
| 20120068193 | STRUCTURE AND METHOD FOR INCREASING STRAIN IN A DEVICE A method and structure are disclosed for increasing strain in a device, specifically an n-type field effect transistor (NFET) complementary metal-oxide-semiconductor (CMOS) device. Embodiments of this invention include growing an epitaxial layer, performing a cold carbo... | 03/22/2012 |
| 20120068231 | VERTICAL DISCRETE DEVICES WITH TRENCH CONTACTS AND ASSOCIATED METHODS OF MANUFACTURING The present technology is related generally to vertical discrete devices with a trench at the topside of the vertical discrete devices. The trench is filled with a conducting material. In this approach, a drain or cathode of the vertical discrete devices is electrically... | 03/22/2012 |
| 20120068253 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME According to one embodiment, a nonvolatile semiconductor memory device includes a memory region and a non-memory region. The memory region includes a stacked structural body, a semiconductor pillar, a memory layer, an inner insulating film and an outer insulating film. ... | 03/22/2012 |
| 20120068233 | TRANSISTORS HAVING STRESSED CHANNEL REGIONS AND METHODS OF FORMING TRANSISTORS HAVING STRESSED CHANNEL REGIONS A method of forming a field effect transistor and a field effect transistor. The method includes (a) forming gate stack on a silicon layer of a substrate; (b) forming two or more SiGe filled trenches in the silicon layer on at least one side of the gate stack, adjacent ... | 03/22/2012 |
| 20120068149 | APPARATUS OF MEMORY ARRAY USING FINFETS In one or more embodiments, a semiconductor device a FinFET device and a second device. In one or more embodiments, the semiconductor device has a contact element coupled between a surface of the fin and the second device.... | 03/22/2012 |
| 20120068260 | Method for producing a structure element and semiconductor component comprising a structure element A semiconductor component includes a semiconductor body having a surface and a cutout in the semiconductor body. The cutout extends from the surface of the semiconductor body into the semiconductor body in a direction perpendicular to the surface. The cutout has a base ... | 03/22/2012 |
