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| Application No. | Application Title | Issue Date |
| 20120025320 | COMPLEMENTARY METAL OXIDE SEMICONDUCTOR TRANSISTOR AND FABRICATING METHOD THEREOF A fabricating method of CMOS transistor includes following steps. A first gate and a second gate are formed on a substrate. A gate insulator is formed on the substrate to cover the first and second gates. A first source, a first drain, a second source, and a second drai... | 02/02/2012 |
| 20110248348 | Hybrid Gate Process For Fabricating Finfet Device Provided is a method of fabricating a semiconductor device that includes forming first and second fins over first and second regions of a substrate, forming first and second gate structures over the first and second fins, the first and second gate structures including f... | 10/13/2011 |
| 20110215412 | STRUCTURE AND METHOD TO FABRICATE pFETS WITH SUPERIOR GIDL BY LOCALIZING WORKFUNCTION A semiconductor structure and a method of forming the same are provided in which the gate induced drain leakage is controlled by introducing a workfunction tuning species within selected portions of a pFET such that the gate/SD (source/drain) overlap area of the pFET is... | 09/08/2011 |
| 20110180846 | Method for Forming Antimony-Based FETs Monolithically An integrated circuit structure includes a substrate and a first and a second plurality of III-V semiconductor layers. The first plurality of III-V semiconductor layers includes a first bottom barrier over the substrate; a first channel layer over the first bottom barri... | 07/28/2011 |
| 20110175172 | MANUFACTURING A SEMICONDUCTOR DEVICE There is provided a semiconductor device including: a semiconductor substrate; a gate insulating film formed on the semiconductor substrate; a work function control layer formed on the gate insulating film; a first silicide layer formed on the work function control laye... | 07/21/2011 |
| 20110073954 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME In a semiconductor substrate in a first section, a channel region having an impurity concentration peak in an interior of the semiconductor substrate is formed, and in the semiconductor substrate in a second section and a third section, channel regions having an impurit... | 03/31/2011 |
| 20110018068 | INTEGRATED DEVICE INCORPORATING LOW-VOLTAGE COMPONENTS AND POWER COMPONENTS, AND PROCESS FOR MANUFACTURING SUCH DEVICE An integrated device includes: a semiconductor body having a first, depressed, portion and second portions which project from the first portion; a STI structure, extending on the first portion of the semiconductor body, which delimits laterally the second portions and h... | 01/27/2011 |
| 20100327365 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE A method of manufacturing a semiconductor device includes: forming a gate insulating film over a semiconductor substrate; forming a mask that has an opening at a position corresponding to the gate insulating film formed in an NMOSFET forming region and covers the gate i... | 12/30/2010 |
| 20100258880 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME A semiconductor device includes: an n-channel MIS transistor and a p-channel MIS transistor. An n-channel MIS transistor includes: a first gate insulating film having an amorphous layer or an epitaxial layer formed on a p-type semiconductor region between a first source... | 10/14/2010 |
| 20100187612 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME A semiconductor device according to an embodiment of the present invention includes an N-type transistor formed in a first region on a substrate, and a P-type transistor formed in a second region on the substrate. The device includes the substrate, a first gate insulati... | 07/29/2010 |
| 20100148273 | CMOS TRANSISTORS WITH DIFFERENTIAL OXYGEN CONTENT HIGH-K DIELECTRICS An NFET containing a first high-k dielectric portion and a PFET containing a second high-k gate dielectric portion are formed on a semiconductor substrate. A gate sidewall nitride is formed on the gate of the NFET, while the sidewalls of the PFET remain free of the gate... | 06/17/2010 |
| 20090309164 | STRUCTURE AND METHOD TO INTEGRATE DUAL SILICIDE WITH DUAL STRESS LINER TO IMPROVE CMOS PERFORMANCE The present invention provides a semiconducting device including a substrate including a semiconducting surface having an n-type device in a first device region and a p-type device in a second device region, the n-type device including a first gate structure present ove... | 12/17/2009 |
| 20090294801 | METHODS OF INTEGRATING REVERSE eSiGe ON NFET AND SiGe CHANNEL ON PFET, AND RELATED STRUCTURE Methods of integrating reverse embedded silicon germanium (SiGe) on an NFET and SiGe channel on a PFET, and a related structure are disclosed. One method may include providing a substrate including an NFET area and a PFET area; performing a single epitaxial growth of a ... | 12/03/2009 |
| 20090256173 | COMPLEMENTARY FIELD EFFECT TRANSISTORS HAVING EMBEDDED SILICON SOURCE AND DRAIN REGIONS A method is provided of fabricating complementary stressed semiconductor devices, e.g., an NFET having a tensile stressed channel and a PFET having a compressive stressed channel. In such method, a first semiconductor region having a lattice constant larger than silicon... | 10/15/2009 |
| 20090230479 | Hybrid Process for Forming Metal Gates of MOS Devices A semiconductor structure includes a first MOS device including a first gate, and a second MOS device including a second gate. The first gate includes a first high-k dielectric over a semiconductor substrate; a second high-k dielectric over the first high-k dielectric; ... | 09/17/2009 |
| 20090189225 | SEMICONDUCTOR DEVICE AND ITS FABRICATION METHOD A semiconductor device includes a first MIS transistor, and a second MIS transistor having a threshold voltage higher than that of the first MIS transistor. The first MIS transistor includes a first gate insulating film made of a high-k insulating film formed on a first... | 07/30/2009 |
| 20090020823 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME A semiconductor device of the present invention includes a first transistor, a first stress-inducing film, a first insulating film, and a second insulating film. The first transistor is formed in a first active region of a semiconductor substrate, and includes a first g... | 01/22/2009 |
| 20080283936 | SILICON GERMANIUM FLOW WITH RAISED SOURCE/DRAIN REGIONS IN THE NMOS Provided is a method for manufacturing a semiconductor device that includes a substrate having a PMOS device region and NMOS device region. A first gate structure including a first hardmask and a second gate structure including a second hardmask are formed in the region... | 11/20/2008 |
| 20080272438 | CMOS Circuits with High-K Gate Dielectric A CMOS structure is disclosed in which a first type FET contains a liner, which liner has oxide and nitride portions. The nitride portions are forming the edge segments of the liner. These nitride portions are capable of preventing oxygen from reaching the high-k dielec... | 11/06/2008 |
| 20080258181 | Hybrid Substrates and Methods for Forming Such Hybrid Substrates Hybrid substrates characterized by semiconductor islands of different crystal orientations and methods of forming such hybrid substrates. The methods involve using a SIMOX process to form an insulating layer. The insulating layer may divide the islands of at least one o... | 10/23/2008 |
| 20080237635 | STRUCTURE AND METHOD FOR STRAINED TRANSISTOR DIRECTLY ON INSULATOR A semiconductor device (10) comprising a substrate (12) and an oxide layer (14) formed over the substrate is provided. The semiconductor device further includes a first semiconductor layer (16) having a first lattice constant formed directly ... | 10/02/2008 |
| 20080217657 | Power Semiconductor Device and Method of Manufacturing a Power Semiconductor Device A semiconductor power switch having an array of basic cells in which peripheral regions in the active drain region extend beside the perimeter of the base-drain junction, the peripheral regions being of higher dopant density than the rest of the second drain layer. Inte... | 09/11/2008 |
| 20080217695 | Heterogeneous Semiconductor Substrate A substrate comprising a first region of a first semiconductor and a second region of second semiconductor, wherein the first semiconductor and the second semiconductor are different, is disclosed. The substrate is particularly supportive of p-channel MOSFETs and n-chan... | 09/11/2008 |
| 20080217696 | METHOD AND STRUCTURE FOR CONTROLLING STRESS IN A TRANSISTOR CHANNEL A method for manufacturing a device including an n-type device and a p-type device. In an aspect of the invention, the method involves forming a shallow-trench-isolation oxide (STI) isolating the n-type device from the p-type device. The method further involves adjustin... | 09/11/2008 |
| 20080211033 | Reducing oxidation under a high K gate dielectric A metal layer is formed on a dielectric layer, which is formed on a substrate. After forming a masking layer on the metal layer, the exposed sides of the dielectric layer are covered with a polymer diffusion barrier.... | 09/04/2008 |
| 20080203489 | Ensuring Migratability of Circuits by Masking Portions of the Circuits While Improving Performance of Other Portions of the Circuits Mechanisms for ensuring the migratability of circuits into future technologies while minimizing fabrication costs and maintaining or improving power efficiency are provided. A mask layer is introduced to portions of the integrated circuit prior to a stress inducing laye... | 08/28/2008 |
| 20080157211 | Integrated circuit and method of forming the same An integrated circuit includes a transistor of a first type with a first gate electrode and a transistor of a second type with a second gate electrode. The first gate electrode is formed in a first gate groove that is defined in a semiconductor substrate, and the second... | 07/03/2008 |
| 20080135879 | METHOD OF FABRICATING CMOS TRANSISTOR AND CMOS TRANSISTOR FABRICATED THEREBY In a method of fabricating a CMOS transistor, and a CMOS transistor fabricated according to the method, the characteristics of first and second conductivity type MOS transistors are both simultaneously improved. At the same time, the fabrication process is simplified by... | 06/12/2008 |
| 20080116518 | METAL-OXIDE-SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF The present invention provides a device for ESD protection and voltage stabilizing in order to let chip space be put in better utilization. During different conditions (i.e. ESD current occurrences and normal operation), identical elements of the device are used both fo... | 05/22/2008 |
| 20080099794 | SEMICONDUCTOR DEVICE COMPRISING NMOS AND PMOS TRANSISTORS WITH EMBEDDED SI/GE MATERIAL FOR CREATING TENSILE AND COMPRESSIVE STRAIN By forming a substantially continuous and uniform semiconductor alloy in one active region while patterning the semiconductor alloy in a second active region so as to provide a base semiconductor material in a central portion thereof, different types of strain may be in... | 05/01/2008 |
| 20080009114 | HYBRID CRYSTAL ORIENTATION CMOS STRUCTURE FOR ADAPTIVE WELL BIASING AND FOR POWER AND PERFORMANCE ENHANCEMENT The present invention provides a semiconducting structure including a substrate having an SOI region and a bulk-Si region, wherein the SOI region and the bulk-Si region have a same or differing crystallographic orientation; an isolation region separating the SOI region ... | 01/10/2008 |
| 20070278588 | Semiconductor device and method for manufacturing the same A semiconductor device manufacturing method has forming a gate insulation film on a silicon substrate having an nMOS transistor region and a pMOS transistor region, forming a first metal film on the gate insulation film and thereby forming a gate electrode of the nMOS t... | 12/06/2007 |
| 20070272948 | INVERTER WITH DUAL-GATE ORGANIC THIN-FILM TRANSISTOR Provided is an inverter having a new structure capable of easily controlling a threshold voltage according to position in fabricating an inverter circuit on a plastic substrate using an organic semiconductor. A driver transistor is formed with a dual-gate structure and ... | 11/29/2007 |
| 20070262392 | LOCOS on SOI and HOT semiconductor device and method for manufacturing One or more local oxidation of silicon (LOCOS) regions may be formed that apply compressive strain to a channel of a field-effect transistor such as a P-type field-effect transistor (PFET) or other circuit element of a semiconductor device. For instance, a pair of LOCOS... | 11/15/2007 |
| 20070262361 | STRUCTURE AND METHOD FOR MANUFACTURING STRAINED SILICON DIRECTLY-ON-INSULATOR SUBSTRATE WITH HYBRID CRYSTALLINE ORIENTATION AND DIFFERENT STRESS LEVELS The present invention provides a strained Si directly on insulator (SSDOI) substrate having multiple crystallographic orientations and a method of forming thereof. Broadly, but in specific terms, the inventive SSDOI substrate includes a substrate; an insulating layer at... | 11/15/2007 |
| 20070218636 | Method for forming ultra thin low leakage multi gate devices using a masking layer over the semiconductor substrate The present invention provides a method for manufacturing a semiconductor device having multiple gate dielectric thickness layers. The method, in one embodiment, includes forming a masking layer over a semiconductor substrate in a first active region and a second active... | 09/20/2007 |
| 20070181951 | Selective CESL structure for CMOS application A PMOS device less affected by negative bias time instability (NBTI) and a method for forming the same are provided. The PMOS device includes a barrier layer over at least a portion of a gate structure, a gate spacer, and source/drain regions of a PMOS device. A stresse... | 08/09/2007 |
| 20070111452 | FABRICATING METHOD OF CMOS AND MOS DEVICE A complementary metal-oxide-semiconductor (CMOS) device comprising a substrate, a first type of metal-oxide-semiconductor (MOS) transistor, a second type of MOS transistor, an etching stop layer, a first stress layer and a second stress layer is provided. The substrate ... | 05/17/2007 |
| 20070063251 | Semiconductor product including logic, non-volatile memory and volatile memory devices and method for fabrication thereof A semiconductor product and a method for fabricating the semiconductor product employ a semiconductor substrate. The semiconductor substrate has a logic region having a logic device formed therein, a non-volatile memory region having a non-volatile memory device formed ... | 03/22/2007 |
