Class 257/E21.646 - Dynamic random access memory structures (DRAM) (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E21.645. This subclass
No. of applications: 222
Last issue date: 03/22/2012

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Application No.	Application Title	Issue Date
20120068237	SELF-ALIGNED STRAP FOR EMBEDDED CAPACITOR AND REPLACEMENT GATE DEVICES After forming a planarization dielectric layer in a replacement gate integration scheme, disposable gate structures are removed and a stack of a gate dielectric layer and a gate electrode layer is formed within recessed gate regions. Each gate electrode structure is the...	03/22/2012
20120070950	Method of Manufacturing a Semiconductor Device A semiconductor device includes a substrate having a first area and a second area, a first active structure disposed in the first area, a second active structure disposed in the second area, a first transistor disposed in the first area and a second transistor disposed ...	03/22/2012
20120025288	SOI Trench DRAM Structure With Backside Strap In one exemplary embodiment, a semiconductor structure including: a silicon-on-insulator substrate having of a top silicon layer overlying an insulation layer, where the insulation layer overlies a bottom silicon layer; a capacitor disposed at least partially in the ins...	02/02/2012
20120012913	SEMICONDUCTOR DEVICE INCLUDING VERTICAL TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME A semiconductor device including a vertical transistor and a method for manufacturing the same may reduce a cell area in comparison with a conventional layout of 8F2 and 6F2. Also, the method does not require forming a bit line contact, a storage node contact or a landi...	01/19/2012
20120009743	DYNAMIC RANDOM ACCESS MEMORY HAVING JUNCTION FIELD EFFECT TRANSISTOR CELL ACCESS DEVICE A method of fabricating a dynamic random access memory (DRAM) can include depositing a semiconductor electrode layer in contact with a surface of a semiconductor substrate; patterning the electrode layer to form a plurality of access junction field effect transistor (JF...	01/12/2012
20110291170	Semiconductor Device Comprising a Buried Capacitor Formed in the Contact Level In a semiconductor device, capacitors may be formed so as to be in direct contact with a transistor by using a shared transistor region, such as a drain region or a source region of closely spaced transistors, as one capacitor electrode, while the other capacitor electr...	12/01/2011
20110291166	INTEGRATED CIRCUIT WITH FINFETS AND MIM FIN CAPACITOR An integrated circuit having finFETs and a metal-insulator-metal (MIM) fin capacitor and methods of manufacture are disclosed. A method includes forming a first finFET comprising a first dielectric and a first conductor; forming a second finFET comprising a second diele...	12/01/2011
20110287595	SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are dispose...	11/24/2011
20110284941	METHOD OF FABRICATING A SEMICONDUCTOR DEVICE A semiconductor device includes: a transistor including source and drain diffusion-layers, a gate insulating film and a gate electrode; first and second plugs formed in a first interlayer-insulating film and connected to the source and drain diffusion-layers, respective...	11/24/2011
20110260231	MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME The present application discloses a memory device and a method for manufacturing the same. The memory device comprising an MOSFET formed in a semiconductor layer and a capacitor structure below the MOSFET, wherein the capacitor structure comprises two capacitor electrod...	10/27/2011
20110260230	CELL WITH SURROUNDING WORD LINE STRUCTURES AND MANUFACTURING METHOD THEREOF A memory cell with surrounding word line structures includes an active area; a plurality of first trenches formed on the active area in a first direction, each first trench has a bit line on a sidewall therein; a plurality of second trenches formed on the active area in...	10/27/2011
20110256678	METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE A method for manufacturing a semiconductor device is disclosed. A method for manufacturing a semiconductor device includes forming a device isolation structure for defining an active region, forming a buried word line traversing the active region, forming one or more in...	10/20/2011
20110230023	DRAM CELL WITH ENHANCED CAPACITOR AREA AND THE METHOD OF MANUFACTURING THE SAME A dynamic random access memory (DRAM) cell and the method of manufacturing the same are provided. The DRAM cell includes a cell transistor and a cell capacitor. The cell capacitor includes a first, second and third dielectric layer, and a first, second and third capacit...	09/22/2011
20110223730	METHOD OF MANUFACTURING SEMICONDUCTOR CIRCUIT DEVICE Provided is a method of manufacturing a semiconductor circuit device including a MOS transistor and a capacitor element in which a gate electrode of a MOS transistor is formed of a first polysilicon film, a capacitor is formed of the first polysilicon film, a capacitor ...	09/15/2011
20110217819	DRAM LAYOUT WITH VERTICAL FETS AND METHOD OF FORMATION DRAM cell arrays having a cell area of less than about 4F²comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The buried bit lines comprise a silicide material and are provided below a surface of the substrate...	09/08/2011
20110211399	METHOD OF MANUFACTURING A VERTICAL-TYPE SEMICONDUCTOR DEVICE AND METHOD OF OPERATING A VERTICAL-TYPE SEMICONDUCTOR DEVICE In a vertical-type semiconductor device, a method of manufacturing the same and a method of operating the same, the vertical-type semiconductor device includes a single-crystalline semiconductor pattern having a pillar shape provided on a substrate, a gate surrounding s...	09/01/2011
20110199813	NON-VOLATILE MEMORY DEVICE HAVING 3D STRUCTURE AND METHOD FOR FABRICATING THE SAME A non-volatile memory device having a three-dimensional (3D) structure includes a plurality of line-type horizontal electrode structures configured to include a plurality of interlayer dielectric layers and a plurality of horizontal electrodes that are alternately stack...	08/18/2011
20110195552	METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE A semiconductor device includes a transistor. A gate insulating film of the transistor contains oxygen and nitrogen atoms. The gate insulating film does not contain the nitrogen atoms in a first face thereof being in a contact with the semiconductor layer, and in a seco...	08/11/2011
20110180862	EMBEDDED DYNAMIC RANDOM ACCESS MEMORY DEVICE AND METHOD Embodiments of the invention provide an integrated circuit for an embedded dynamic random access memory (eDRAM), a semiconductor-on-insulator (SOI) wafer in which such an integrated circuit may be formed, and a method of forming an eDRAM in such an SOI wafer. One embodi...	07/28/2011
20110177660	DEEP TRENCH CAPACITOR FOR SOI CMOS DEVICES FOR SOFT ERROR IMMUNITY A semiconductor structure is disclosed. The semiconductor structure includes an active semiconductor layer, a semiconductor device having a gate disposed on top of the active semiconductor layer, and source and drain regions and a body/channel region disposed within the...	07/21/2011
20110175083	Semiconductor Device A semiconductor device has a non-volatile memory cell including a write transistor which includes an oxide semiconductor and has small leakage current in an off state (off-state current) between a source and a drain, a read transistor including a semiconductor material ...	07/21/2011
20110170336	DRAM Device and Manufacturing Method Thereof The present invention relates to a DRAM device having 4F2 size cells and a method for fabricating the same. The DRAM device comprises plural word lines arranged parallel to each other in one direction, plural bit lines arranged parallel to each other and in an intersect...	07/14/2011
20110169065	METHOD AND STRUCTURE FOR FORMING CAPACITORS AND MEMORY DEVICES ON SEMICONDUCTOR-ON-INSULATOR (SOI) SUBSTRATES A device is provided that includes memory, logic and capacitor structures on a semiconductor-on-insulator (SOI) substrate. In one embodiment, the device includes a semiconductor-on-insulator (SOI) substrate having a memory region and a logic region. Trench capacitors ar...	07/14/2011
20110169061	Semiconductor device and method for manufacturing the same The semiconductor device comprises a first region, a guard ring surrounding the first region, and a second region outside of the guard ring. The first region includes a first electrode made of a first film which has conductivity. A surface of the first electrode in the ...	07/14/2011
20110165744	MEMORY ARRAY WITH ULTRA-THIN ETCHED PILLAR SURROUND GATE ACCESS TRANSISTORS AND BURIED DATA/BIT LINES A memory array with data/bit lines extending generally in a first direction formed in an upper surface of a substrate and access transistors extending generally upward and aligned generally atop a corresponding data/bit line. The access transistors have a pillar extendi...	07/07/2011
20110156116	RELAXED-PITCH METHOD OF ALIGNING ACTIVE AREA TO DIGIT LINE According to one aspect of the invention, a memory device is disclosed. The memory device comprises a substantially linear active area comprising a source and at least two drains defining a first axis. The memory device further comprises at least two substantially paral...	06/30/2011
20110156118	SEMICONDUCTOR DEVICE WITH VERTICAL CELLS AND FABRICATION METHOD THEREOF A method for fabricating a semiconductor substrate includes defining an active region by forming a device isolation layer over the substrate, forming a first trench dividing the active region into a first active region and a second active region, forming a buried bit li...	06/30/2011
20110140187	Methods of Forming Vertical Field Effect Transistors, Vertical Field Effect Transistors, And DRAM Cells A method of forming a vertical field effect transistor includes etching an opening into semiconductor material. Sidewalls and radially outermost portions of the opening base are lined with masking material. A semiconductive material pillar is epitaxially grown to within...	06/16/2011
20110133310	INTEGRATED CIRCUIT AND A METHOD USING INTEGRATED PROCESS STEPS TO FORM DEEP TRENCH ISOLATION STRUCTURES AND DEEP TRENCH CAPACITOR STRUCTURES FOR THE INTEGRATED CIRCUIT Disclosed is an integrated circuit having at least one deep trench isolation structure and a deep trench capacitor. A method of forming the integrated circuit incorporates a single etch process to simultaneously form first trench(s) and a second trenches for the deep tr...	06/09/2011
20110121372	EDRAM Architecture A process for manufacturing an eDRAM device comprises fabricating semiconductor features on a semiconductor substrate, the semiconductor substrate including a DRAM area and logic area. The process also includes fabricating a first conductive layer in the DRAM area and i...	05/26/2011
20110101499	SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME A semiconductor device and a method for fabricating a semiconductor device are provided. The method for fabricating a semiconductor device includes forming an isolation layer over a semiconductor substrate defining first and second regions, etching the isolation layer a...	05/05/2011
20110092034	ZERO CAPACITOR RAM WITH RELIABLE DRAIN VOLTAGE APPLICATION AND METHOD FOR MANUFACTURING THE SAME The following discloses and describes a zero capacitor RAM as well as a method for manufacturing the same. The zero capacitor RAM includes an SOI substrate. This SOI substrate is composed of a stacked structure of a silicon substrate, an embedded insulation film and a s...	04/21/2011
20110092035	Formation of high sheet resistance resistors and high capacitance capacitors by a single polysilicon process A semiconductor device includes a transistor, a capacitor and a resistor wherein the capacitor includes a doped polysilicon layer to function as a bottom conductive layer with a salicide block (SAB) layer as a dielectric layer covered by a Ti/TiN layer as a top conducti...	04/21/2011
20110079836	DRAM CELL WITH DOUBLE-GATE FIN-FET, DRAM CELL ARRAY AND FABRICATION METHOD THEREOF A transistor structure includes a semiconductor substrate having a top surface and sidewalls extending downward from the top surface, wherein each of the sidewall comprises a vertical upper sidewall surface and a lower sidewall recess laterally etched into the semicondu...	04/07/2011
20110073925	SEMICONDUCTOR DEVICE WITH BURIED BIT LINES INTERCONNECTED TO ONE-SIDE-CONTACT AND FABRICATION METHOD THEREOF A semiconductor device with reduced resistance of a buried bit line, and a method for fabricating the same. The method for fabricating a semiconductor device includes etching a semiconductor substrate to form a plurality of active regions which are separated from one an...	03/31/2011
20110070704	SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME It is disclosed a semiconductor device including a silicon substrate, provided with a plurality of cell active regions in a call region, an element isolation groove, formed in a portion, between any two of the plurality of cell active region, of the silicon substrate, a...	03/24/2011
20110049595	METHOD FOR FORMING MEMORY CELL TRANSISTOR A method for forming a memory cell transistor is disclosed which includes providing a substrate, forming a trench structure in the substrate, depositing a conductive substance on the surface of the substrate to form a conductive member inside the trench structure, formi...	03/03/2011
20110042731	STRUCTURE AND METHOD OF FORMING ENHANCED ARRAY DEVICE ISOLATION FOR IMPLANTED PLATE EDRAM A method for forming a memory device in a semiconductor on insulator substrate is provided, in which a protective oxide that is present on the sidewalls of the trench protects the first semiconductor layer, i.e., SOI layer, of the semiconductor on insulator substrate du...	02/24/2011
20110037111	SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME The invention relates to a semiconductor device and a method of fabricating the same, wherein a storage node contact hole is made large to solve any problem caused during etching a storage node contact hole with a small CD, a landing plug is formed to lower plug resista...	02/17/2011
20110001174	Memory Cells, And Methods Of Forming Memory Cells Some embodiments include memory cells that contain floating bodies and diodes. The diodes may be gated diodes having sections doped to a same conductivity type as the floating bodies, and such sections of the gated diodes may be electrically connected to the floating bo...	01/06/2011

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Class 257/E21.646 - Dynamic random access memory structures (DRAM) (EPO)