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Mark Twain (Samuel L. Clemens) received Patent No. 121,992 for "An Improvement in Adjustable and Detachable Straps for Garments." He later received two more patents: one for a self-pasting scrapbook and one for a game to help players remember important historical dates.

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Class 257/E21.635 - With particular manufacturing method of gate conductor, e.g., particular materials, shapes (EPO)


Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E21.632. This subclass
No. of applications: 30
Last issue date: 05/03/2012


Application No.Application TitleIssue Date
20120104507METHOD FOR GROWING STRAIN-INDUCING MATERIALS IN CMOS CIRCUITS IN A GATE FIRST FLOW
A method of manufacturing a complementary metal oxide semiconductor (CMOS) circuit, in which the method includes a reactive ion etch (RIE) of a CMOS circuit substrate that forms recesses, the CMOS circuit substrate including: an n-type field effect transistor (n-FET) re... 		05/03/2012
20110186926Semiconductor device having a lightly doped semiconductor gate and method for fabricating same
According to one embodiment, a semiconductor device comprises a high-k gate dielectric overlying a well region having a first conductivity type formed in a semiconductor body, and a semiconductor gate formed on the high-k gate dielectric. The semiconductor gate is light... 		08/04/2011
20110171794TRANSISTOR FORMATION USING CAPPING LAYER
A method of transistor formation using a capping layer in complimentary metal-oxide semiconductor (CMOS) structures is provided, the method including: depositing a conductive layer over an n-type field effect transistor (nFET) and over a p-type field effect transistor (... 		07/14/2011
20110147851Method For Depositing Gate Metal For CMOS Devices
A semiconductor device comprises a substrate, a channel region, and a gate formed in association with the channel region. In one exemplary embodiment, the gate comprises a first material that is formed void free on an interior surface of a gate trench of the gate. A wid... 		06/23/2011
20110115027STRUCTURE AND METHOD TO OBTAIN EOT SCALED DIELECTRIC STACKS
Equivalent oxide thickness (EOT) scaled high k/metal gate stacks are provided in which the capacitance bottleneck of the interfacial layer is substantially eliminated, with minimal compromise on the mobility of carriers in the channel of the device. In one embodiment, t... 		05/19/2011
20110042750CONTROLLING GATE FORMATION FOR HIGH DENSITY CELL LAYOUT
Methods of forming a semiconductor structure and the semiconductor structure are disclosed. In one embodiment, a method includes forming a gate dielectric layer over a substrate, forming a gate electrode layer over the gate dielectric layer, and etching the gate electro... 		02/24/2011
20100330790TECHNIQUE FOR EXPOSING A PLACEHOLDER MATERIAL IN A REPLACEMENT GATE APPROACH BY MODIFYING A REMOVAL RATE OF STRESSED DIELECTRIC OVERLAYERS
In a replacement gate approach, the sacrificial gate material is exposed on the basis of enhanced process uniformity, for instance during a wet chemical etch step or a CMP process, by forming a modified portion in the interlayer dielectric material by ion implantation. ... 		12/30/2010
20100330757ENHANCED CAP LAYER INTEGRITY IN A HIGH-K METAL GATE STACK BY USING A HARD MASK FOR OFFSET SPACER PATTERNING
When forming transistor elements on the basis of sophisticated high-k metal gate structures, the efficiency of a replacement gate approach may be enhanced by more efficiently adjusting the gate height of transistors of different conductivity type when the dielectric cap... 		12/30/2010
20100285642Method of Doping Impurity Ions in Dual Gate and Method of Fabricating the Dual Gate using the same
A method of doping impurity ions in a dual gate includes doping first conductivity type impurity ions in a gate conductive layer over a semiconductor substrate having a first region and a second region, wherein the doping is performed with a concentration gradient so th... 		11/11/2010
20100279496MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
To improve productivity and performance of a CMISFET including a high-dielectric-constant gate insulating film and a metal gate electrode. An Hf-containing insulating film for a gate insulating film is formed over the main surface of a semiconductor substrate. A metal n... 		11/04/2010
20100221878Hybrid Metal Fully Silicided (FUSI) Gate
A semiconductor device and system for a hybrid metal fully silicided (FUSI) gate structure is disclosed. The semiconductor system comprises a PMOS gate structure, the PMOS gate structure including a first high-κ dielectric layer, a P-metal layer, a mid-gap metal layer,... 		09/02/2010
20100216287METHOD FOR REMOVING HARD MASKS ON GATES IN SEMICONDUCTOR MANUFACTURING PROCESS
A method for removing hard masks on gates in a semiconductor manufacturing process is conducted as follows. First of all, a first gate and a second gate with hard masks are formed on a semiconductor substrate, wherein the second gate is larger than the first gate. The f... 		08/26/2010
20100197128CMOS Integration with Metal Gate and Doped High-K Oxides
A method and apparatus are described for fabricating single metal gate electrodes (35, 36) over a high-k gate dielectric layer (31, 32) that is separately doped in the PMOS and NMOS device areas (96, 97) by forming first capping oxide layer (23		08/05/2010
20100178754METHOD OF MANUFACTURING CMOS TRANSISTOR
A method of manufacturing a complementary metal-oxide semiconductor (CMOS) transistor includes: forming a semiconductor layer in which an n-MOS transistor region and a p-MOS transistor region are defined; forming an insulation layer on the semiconductor layer; forming a... 		07/15/2010
20100164008METHOD FOR INTEGRATION OF REPLACEMENT GATE IN CMOS FLOW
Semiconductor devices and fabrication methods are provided, in which metal transistor replacement gates are provided for CMOS transistors. The process provides dual or differentiated work function capability (e.g., for PMOS and NMOS transistors) in CMOS processes.... 		07/01/2010
20100129968Semiconductor Devices and Methods of Manufacture Thereof
Semiconductor devices with transistors having different gate dielectric materials and methods of manufacture thereof are disclosed. One embodiment includes a semiconductor device including a workpiece, the workpiece including a first region and a second region proximate... 		05/27/2010
20100087055METHOD FOR GATE HEIGHT CONTROL IN A GATE LAST PROCESS
Provided is a method that includes forming first and second gate structures in first and second regions, respectively, the first gate structure including a first hard mask layer having a first thickness and the second gate structure including a second hard mask layer ha... 		04/08/2010
20100078729SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE
A semiconductor device includes a transistor configuration including first and second gate electrodes, each of the first and second gate electrodes having at least a bottom layer and an upper layer including polycrystalline silicon grains, wherein the first gate electro... 		04/01/2010
20100059827SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A first and second gate electrodes are formed on a first and second active regions, respectively. The first and second gate electrodes have a first and second metal-containing conductive films, respectively. The first and second metal-containing conductive films are for... 		03/11/2010
20100044798TRANSISTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME
A transistor device is provided that includes a substrate, a first channel region formed in a first portion of the substrate and being doped with a dopant of a first type of conductivity, a second channel region formed in a second portion of the substrate and being dope... 		02/25/2010
20090317951SEMICONDUCTOR DEVICE
A semiconductor device has an n-channel MIS transistor and a p-channel MIS transistor on a substrate. The n-channel MIS transistor includes a p-type semiconductor region formed on the substrate, a lower layer gate electrode which is formed via a gate insulating film abo... 		12/24/2009
20090275179COMPLEMENTARY METAL OXIDE SEMICONDUCTOR DEVICE WITH AN ELECTROPLATED METAL REPLACEMENT GATE
Disclosed herein are embodiments of a method of forming a complementary metal oxide semiconductor (CMOS) device that has at least one high aspect ratio gate structure with a void-free and seam-free metal gate conductor layer positioned on top of a relatively thin high-k... 		11/05/2009
20090065873Semiconductor device and method of fabricating metal gate of the same
Provided is a semiconductor device that comprises a metal gate having a low sheet resistance characteristic and a high diffusion barrier characteristic and a method of fabricating the metal gate of the semiconductor device. The semiconductor device includes a metal gate... 		03/12/2009
20090020821DUAL WORKFUNCTION SEMICONDUCTOR DEVICE
A dual workfunction semiconductor device which comprises a first and second control electrode comprising a metal-semiconductor compound, e.g. a silicide or a germanide, and a dual workfunction semiconductor device thus obtained are disclosed. In one aspect, the method c... 		01/22/2009
20090011555Method of manufacturing CMOS integrated circuit
In a method of manufacturing a CMOS integrated circuit according to the present invention, a PSD step (step of forming P-type source/drain regions) is first carried out, and an NSD step (step of forming N-type source/drain regions) is thereafter carried out, in order to... 		01/08/2009
20080283927Tunable stressed polycrystalline silicon on dielectrics in an integrated circuit
System and method for creating stressed polycrystalline silicon in an integrated circuit. A preferred embodiment comprises manufacturing an integrated circuit, comprising forming a trench in an integrated circuit substrate, forming a cavity within the integrated circuit... 		11/20/2008
20080261360METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE
In a method of manufacturing a semiconductor device, a gate insulation layer is formed on a substrate including a first channel of a first conductive type and a second channel of a second conductive type different from the first conductive type. A first conductive layer... 		10/23/2008
20070298560Semiconductor Device
A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected from ... 		12/27/2007
20070231990CMOS (COMPLEMENTARY METAL OXIDE SEMICONDUCTOR) TECHNOLOGY
A method for forming semiconductor transistor. The method comprises providing a structure including (a) a semiconductor region, and (b) first and second dopant source regions on and in direct physical contact with the semiconductor region, wherein each region of the fir... 		10/04/2007
20070224751Embedded Non-Volatile Memory Cell With Charge-Trapping Sidewall Spacers
An IC includes both “volatile” CMOS transistors (FETs) and embedded non-volatile memory (NVM) cells, both including polysilicon gate structures, sidewall oxide layers, sidewall spacer structures, and source/drain regions. The sidewall spacers of both the NVM cells a... 		09/27/2007
 
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