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| Application No. | Application Title | Issue Date |
| 20120126307 | NON-VOLATILE MEMORY AND MANUFACTURING METHOD THEREOF A non-volatile memory and a manufacturing method thereof are provided. The non-volatile memory includes a substrate, a gate structure, a first doped region, a second doped region and a pair of isolation structures. The gate structure is disposed on the substrate. The ga... | 05/24/2012 |
| 20120127795 | NON-VOLATILE MEMORY AND MANUFACTURING METHOD THEREOF AND OPERATING METHOD OF MEMORY CELL A non-volatile memory and a manufacturing method thereof and a method for operating a memory cell are provided. The non-volatile memory includes a substrate, first and second doped regions, a charged-trapping structure, first and second gates and an inter-gate insulatio... | 05/24/2012 |
| 20120126308 | NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME A non-volatile memory device includes a plurality of memory cells stacked along a channel protruded from a substrate, a first select transistor connected to one end of the plurality of memory cells, a first interlayer dielectric layer for being coupled between a source ... | 05/24/2012 |
| 20120104483 | NON-VOLATILE MEMORY AND LOGIC CIRCUIT PROCESS INTEGRATION A method of making a logic transistor in a logic region of a substrate and a non-volatile memory cell in an NVM region of the substrate includes forming a gate dielectric layer on the substrate. A first polysilicon layer is formed on the gate dielectric. The first polys... | 05/03/2012 |
| 20120083086 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR There is provided a semiconductor device including a semiconductor substrate (10), a high concentration diffusion region (22) formed within the semiconductor substrate (10), a first low concentration region (24) that has a lower impurity conc... | 04/05/2012 |
| 20120070951 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREFOR There is provided a semiconductor device including bit lines (14) formed in a semiconductor substrate (10), insulating film lines (18) located on the bit lines (14) to successively run in a length direction of the bit lines (14), gate ... | 03/22/2012 |
| 20120068256 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE An dielectric film is formed above the semiconductor substrate. A first conductive layer is formed in the dielectric film and extending in a first direction. The first conductive layer is connected to a first select transistor. A second conductive layer formed in the di... | 03/22/2012 |
| 20120052672 | METHODS FOR FABRICATING A CELL STRING AND A NON-VOLATILE MEMORY DEVICE INCLUDING THE CELL STRING A method for fabricating a cell string includes forming an interlayer dielectric layer, a sacrificial layer, and a semiconductor pattern on a semiconductor substrate, such that the interlayer dielectric layer and the sacrificial layer are formed in a first direction par... | 03/01/2012 |
| 20120052673 | METHOD FOR FABRICATING NONVOLATILE MEMORY DEVICE A method for fabricating a nonvolatile memory device is disclosed. The method includes forming a first structure for a common source line on a semiconductor substrate, the first structure extending along a first direction, forming a mold structure by alternately stackin... | 03/01/2012 |
| 20120043601 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME In a nonvolatile semiconductor memory device, a stacked body is formed by alternately stacking dielectric films and conductive films on a silicon substrate and a plurality of through holes extending in the stacking direction are formed in a matrix configuration. A shunt... | 02/23/2012 |
| 20120032249 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING NONVOLATILE SEMICONDUCTOR MEMORY DEVICE According to one embodiment, a nonvolatile semiconductor memory device includes a multilayer body, a semiconductor pillar, a memory layer, a first insulating film and a second insulating film. The multilayer body includes a plurality of interelectrode insulating films a... | 02/09/2012 |
| 20120025297 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME According to one embodiment, a nonvolatile semiconductor memory device includes a source region and a drain region provided on a surface area of a semiconductor region, a tunnel insulating film provided on a channel between the source region and the drain region, a char... | 02/02/2012 |
| 20120025287 | Memory Cell, An Array, And A Method for Manufacturing A Memory Cell A memory cell (100) comprising a transistor, the transistor comprising a substrate (101), a first source/drain region (102), a second source/drain region (112), a gate (104) and a gate insulating layer (103) positioned between t... | 02/02/2012 |
| 20120018790 | NON-VOLATILE MEMORY AND FABRICATING METHOD THEREOF A non-volatile memory including a substrate, a stacked gate structure, two doped regions and a plurality of spacers is provided. The stacked gate structure is disposed on the substrate, wherein the stacked gate structure includes a first dielectric layer, a charge stora... | 01/26/2012 |
| 20120018795 | NON-VOLATILE MEMORY AND MANUFACTURING METHOD THEREOF A manufacturing method of a non-volatile memory is disclosed. A gate structure is formed on a substrate and includes a gate dielectric layer and a gate conductive layer. The gate dielectric layer is partly removed, thereby a symmetrical opening is formed among the gate ... | 01/26/2012 |
| 20120012817 | Semiconductor devices and methods of manufacturing an operating same A semiconductor device and methods of manufacturing and operating the semiconductor device may be disclosed. The semiconductor device may comprise different nanostructures. The semiconductor device may have a first element formed of nanowires and a second element formed... | 01/19/2012 |
| 20120008400 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME A non-volatile semiconductor storage device includes: a memory string; a select transistor; and a carrier selection element. The select transistor has one end connected to one end of the memory string. The carrier selection element has one end connected to the other end... | 01/12/2012 |
| 20120009747 | Methods of Manufacturing Nonvolatile Memory Devices Nonvolatile memory devices and methods of manufacturing nonvolatile memory devices are provided. The method includes patterning a bulk substrate to form an active pillar; forming a charge storage layer on a side surface of active pillar; and forming a plurality of gates... | 01/12/2012 |
| 20110316070 | CHARGE TRAPPING NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MAKING The present invention provides a charge trapping non-volatile semiconductor memory device and a method of making the device. The charge trapping non-volatile semiconductor memory device comprises a semiconductor substrate, a source region, a drain region, and, consecuti... | 12/29/2011 |
| 20110312171 | Methods Of Forming Integrated Circuitry Comprising Charge Storage Transistors Methods include forming a charge storage transistor gate stack over semiconductive material. One such stack includes a tunnel dielectric, charge storage material over the tunnel dielectric, a high-k dielectric over the charge storage material, and conductive control gat... | 12/22/2011 |
| 20110309434 | NONVOLATILE MEMORY DEVICE AND MANUFACTURING METHOD THEREOF A nonvolatile memory device and a manufacturing method thereof are provided. The manufacturing method includes the following steps. First, a substrate is provided. Then, a tunneling dielectric layer is formed on the substrate, and a dummy gate is form on the tunneling d... | 12/22/2011 |
| 20110303968 | Nonvolatile Memory Array With Continuous Charge Storage Dielectric Stack An integrated circuit of an array of nonvolatile memory cells has a dielectric stack layer over the substrate, and implanted regions in the substrate under the dielectric stack layer. The dielectric stack layer is continuous over a planar region, that includes locations... | 12/15/2011 |
| 20110303958 | NONVOLATILE SEMICONDUCTOR MEMORY According to one embodiment, a nonvolatile semiconductor memory includes control gates provided in an array form, the control gates passing through the first semiconductor layer, data recording layers between the first semiconductor layer and the control gates, two firs... | 12/15/2011 |
| 20110300682 | CHARGE TRAPPING DEVICES WITH FIELD DISTRIBUTION LAYER OVER TUNNELING BARRIER A memory cell comprising: a semiconductor substrate with a surface with a source region and a drain region disposed below the surface of the substrate and separated by a channel region; a tunneling barrier dielectric structure with an effective oxide thickness of greate... | 12/08/2011 |
| 20110291178 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME According to one embodiment, a semiconductor device includes a substrate, a lower gate layer, a stacked body, a dummy electrode layer, an insulating film, and a channel body. The lower gate layer is provided above the substrate. The stacked body includes a plurality of ... | 12/01/2011 |
| 20110291177 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME A nonvolatile memory device includes a pipe insulation layer having a pipe channel hole, a pipe gate disposed over the pipe insulation layer, a pair of cell strings each having a columnar cell channel, and a pipe channel coupling the columnar cell channels and surroundi... | 12/01/2011 |
| 20110280076 | JUNCTIONLESS TFT NAND FLASH MEMORY A non-volatile memory device includes at least one junctionless transistor and a storage region. The junctionless transistor includes a junctionless, heavily doped semiconductor channel having two dimensions less than 100 nm.... | 11/17/2011 |
| 20110272753 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME In a power feeding region of a memory cell (MC) in which a sidewall-shaped memory gate electrode (MG) of a memory nMIS (Qnm) is provided by self alignment on a side surface of a selection gate electrode (CG) of a selection nMIS (Qnc) via an insulating film, a plug (PM) ... | 11/10/2011 |
| 20110256705 | METHOD FOR FORMING A SPLIT GATE DEVICE A method for forming a semiconductor device includes forming a dielectric layer over a substrate. The method further includes forming a select gate layer over the dielectric layer. The method further includes etching the select gate layer at a first etch rate to form a ... | 10/20/2011 |
| 20110250746 | NONVOLATILE MEMORY DEVICE WITH MULTIPLE BLOCKING LAYERS AND METHOD OF FABRICATING THE SAME A nonvolatile memory device with a blocking layer controlling the transfer of electric charges in a charge storage layer includes the blocking layer having a first blocking layer in contact with the charge storage layer and a second blocking layer over the first blockin... | 10/13/2011 |
| 20110242888 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF The semiconductor device includes the nonvolatile memory cell in the main surface of a semiconductor substrate. The nonvolatile memory cell has a first insulating film over the semiconductor substrate, a conductive film, a second insulating film, the charge storage film... | 10/06/2011 |
| 20110241098 | 3D STACKED ARRAY HAVING CUT-OFF GATE LINE AND FABRICATION METHOD THEREOF A three-dimensional stacked flash memory array having cut-off gate line and a fabricating method of the same are provided. The flash memory array enables to operate two memory cells by each word line, to produce a high integrity without limitation by vertical stacks of ... | 10/06/2011 |
| 20110233649 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE A non-volatile semiconductor memory device includes: a charge accumulation layer (CAL) on a substrate; a memory gate formed onto the substrate through the CAL; a first side gate formed through a first insulating film on a first side of the memory gate; a second side gat... | 09/29/2011 |
| 20110233654 | NANO-CRYSTAL GATE STRUCTURE FOR NON-VOLATILE MEMORY A non-volatile memory device is disclosed having a charge storage layer that incorporates a plurality of nano-crystals. A substrate having a source region and a drain region is provided. Select and control gates are formed on the substrate. The charge storage layer is p... | 09/29/2011 |
| 20110233647 | METHODS FOR FORMING A MEMORY CELL HAVING A TOP OXIDE SPACER Methods for fabricating a semiconductor memory cell that has a spacer layer are disclosed. A method includes forming a plurality of source/drain regions in a substrate where the plurality of source/drain regions are formed between trenches, forming a first oxide layer a... | 09/29/2011 |
| 20110230024 | METHOD FOR MANUFACTURING NON-VOLATILE MEMORY A method for manufacturing a non-volatile memory is provided. The method comprises steps of providing a substrate. Thereafter, a plurality of first doped regions are formed in the substrate and then a plurality of trenches are formed in a portion of the first doped regi... | 09/22/2011 |
| 20110220988 | METHOD FOR MANUFACTURING NAND MEMORY CELLS A method for manufacturing NAND memory cells includes providing a substrate having a first doped region formed therein; forming a first dielectric layer, a storage layer and a patterned hard mask on the substrate; forming a STI in the substrate through the patterned har... | 09/15/2011 |
| 20110220986 | MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME A memory device including a substrate, a conductive layer, a charge storage layer, first and second dopant regions and first and second cell dopant regions is provided. A plurality of trenches is deployed in the substrate. The conductive layer is disposed on the substra... | 09/15/2011 |
| 20110215394 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME According to one embodiment, a semiconductor memory device includes a base, a stacked body, a memory film, a channel body, a contact plug, a global bit line, and a plurality of local bit lines. The base has a substrate and a peripheral circuit formed on the substrate. T... | 09/08/2011 |
| 20110211394 | FIELD EFFECT TRANSISTORS FOR A FLASH MEMORY COMPRISING A SELF-ALIGNED CHARGE STORAGE REGION Storage transistors for flash memory areas in semiconductor devices may be provided on the basis of a self-aligned charge storage region. To this end, a floating spacer element may be provided in some illustrative embodiments, while, in other cases, the charge storage r... | 09/01/2011 |
