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...Daniel Webster invented a "bull plow" to pull out tree stumps. It didn't catch on because it was huge and required four oxen to pull it!
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| Application No. | Application Title | Issue Date |
| 20120126341 | USING LOW PRESSURE EPI TO ENABLE LOW RDSON FET A method for forming an epitaxial layer on a substrate may have the steps of: forming a heavily doped silicon substrate; depositing an epitaxial layer at sub atmospheric pressure on the heavily doped silicon substrate; and implanting dopant into the epitaxial layer by i... | 05/24/2012 |
| 20120128915 | GaAs Wafer And Method For Manufacturing The GaAs Wafer There is provided a method for manufacturing a GaAs wafer comprising: growing a GaAs single crystal by an LEC method; and fabricating a GaAs wafer by slicing the GaAs single crystal obtained by growing the GaAs single crystal, wherein in growing the GaAs single crystal,... | 05/24/2012 |
| 20120129322 | COMPOSITE MATERIAL COMPRISING NANOPARTICLES AND PRODUCTION OF PHOTOACTIVE LAYERS CONTAINING QUATERNARY, PENTANARY AND HIGHER-ORDER COMPOSITE SEMICONDUCTOR NANOPARTICLES A composite material includes at least two components, wherein at least one component is present in the form of nanoparticles, which consist of at least three metals and at least one non-metal and the diameter of which is less than one micrometre, preferably less than 2... | 05/24/2012 |
| 20120126293 | EPITAXIAL SUBSTRATE FOR SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING EPITAXIAL SUBSTRATE FOR SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE An epitaxial substrate, in which a group of group-III nitride layers is formed on a single-crystal silicon substrate so that a crystal plane is approximately parallel to a substrate surface, comprises: a first group-III nitride layer formed of AlN on the base substrate;... | 05/24/2012 |
| 20120126375 | METHOD FOR FORMING METROLOGY STRUCTURES FROM FINS IN INTEGRATED CIRCUITRY A method for forming a plurality of fins on a semiconductor substrate includes depositing a spacer layer to fill in gaps between the plurality of fins, the fins comprising a first material and the spacer layer comprising a second material. A first area is defined where ... | 05/24/2012 |
| 20120129308 | Performance Enhancement in PMOS and NMOS Transistors on the Basis of Silicon/Carbon Material A silicon/germanium material and a silicon/carbon material may be provided in transistors of different conductivity type on the basis of an appropriate manufacturing regime without unduly contributing to overall process complexity. Furthermore, appropriate implantation ... | 05/24/2012 |
| 20120126250 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME The present invention provides a silicon carbide semiconductor device having an ohmic electrode improved in adhesion of a wire thereto by preventing deposition of carbon so as not to form a Schottky contact, as well as a method for manufacturing such a silicon carbide s... | 05/24/2012 |
| 20120129320 | METHOD OF NISIGE EPITAXIAL GROWTH BY INTRODUCING AL INTERLAYER The present invention discloses a method of NiSiGe epitaxial growth by introducing Al interlayer, comprising the deposition of an Al thin film on the surface of SiGe layer, subsequent deposition of a Ni layer on Al thin film and then the annealing process for the reacti... | 05/24/2012 |
| 20120129321 | APPARATUS FOR MANUFACTURING SEMICONDUCTOR A semiconductor device manufacturing apparatus includes a chamber including a reaction space, a substrate disposing unit configured to dispose a substrate within the chamber, a first heating unit configured to optically heat the reaction space and disposed under the cha... | 05/24/2012 |
| 20120108041 | Patterning of Nanostructures A technique for forming nanostructures including a definition of a charge pattern on a substrate and introduction of charged molecular scale sized building blocks (MSSBBs) to a region proximate the charge pattern so that the MSSBBs adhere to the charge pattern to form t... | 05/03/2012 |
| 20120104461 | Semiconductor Heterostructures Having Reduced Dislocation Pile-Ups and Related Methods Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading disloc... | 05/03/2012 |
| 20120104390 | Germanium-Containing Release Layer For Transfer of a Silicon Layer to a Substrate A germanium-containing layer is deposited on a single crystalline bulk silicon substrate in an ambient including a level of oxygen partial pressure sufficient to incorporate 1%-50% of oxygen in atomic concentration. The thickness of the germanium-containing layer is pre... | 05/03/2012 |
| 20120104547 | LATERAL EPITAXIAL GROWN SOI IN DEEP TRENCH STRUCTURES AND METHODS OF MANUFACTURE Deep trench capacitor structures and methods of manufacture are disclosed. The method includes forming a deep trench structure in a wafer comprising a substrate, buried oxide layer (BOX) and silicon (SOI) film. The method further includes forming a plate on a sidewall o... | 05/03/2012 |
| 20120104552 | Capacitors in Integrated Circuits and Methods of Fabrication Thereof In one embodiment, a capacitor includes a first via level having first metal bars and first vias, such that the first metal bars are coupled to a first potential node. The first metal bars are longer than the first vias. Second metal bars and second vias are disposed in... | 05/03/2012 |
| 20120104509 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE A semiconductor device includes: a first conductivity type transistor and a second conductivity type transistor, wherein each of the first conductivity type transistor and the second conductivity type includes a gate insulating film formed on a base, a metal gate electr... | 05/03/2012 |
| 20120108036 | Active Region Patterning in Double Patterning Processes A method includes forming an SRAM cell including a first and a second pull-up transistor and a first and a second pull-down transistor. The step of forming the SRAM cell includes forming a first and a second active region of the first and the second pull-up transistors ... | 05/03/2012 |
| 20120104462 | SEMICONDUCTOR WAFER, METHOD OF PRODUCING SEMICONDUCTOR WAFER, AND ELECTRONIC DEVICE A semiconductor wafer includes a first semiconductor, and a second semiconductor formed directly or indirectly on the first semiconductor. The second semiconductor contains a first impurity atom exhibiting p-type or n-type conductivity, and a second impurity atom select... | 05/03/2012 |
| 20120104347 | METHOD OF FORMING A CHALCOGENIDE MATERIAL, METHODS OF FORMING A RESISTIVE RANDOM ACCESS MEMORY DEVICE INCLUDING A CHALCOGENIDE MATERIAL, AND RANDOM ACCESS MEMORY DEVICES INCLUDING A CHALCOGENIDE MATERIAL A method of forming a chalcogenide material on a surface of a substrate comprising exposing a surface of a substrate to ionized gas clusters from a source gas, the ionized gas clusters comprising at least one chalcogen and at least one electropositive element. A method ... | 05/03/2012 |
| 20120108040 | VAPORIZING POLYMER SPRAY DEPOSITION SYSTEM A vaporizing spray deposition device for forming a thin film includes a processing chamber, a fluid line, and a spray head coupled to the fluid line proximate the processing chamber. The fluid line is configured to transfer a polymer fluid and solvent mixture to the spr... | 05/03/2012 |
| 20120104506 | CMOSFET DEVICE WITH CONTROLLED THRESHOLD VOLTAGE CHARACTERISTICS AND METHOD OF FABRICATING THE SAME There is provided a CMOSFET device with threshold voltage controlled by means of interface dipoles and a method of fabricating the same. A cap layer, for example a very thin layer of poly-silicon, amorphous silicon, or SiO2, is interposed inside high-k gate d... | 05/03/2012 |
| 20120104360 | STRAIN COMPENSATED SHORT-PERIOD SUPERLATTICES ON SEMIPOLAR OR NONPOLAR GAN FOR DEFECT REDUCTION AND STRESS ENGINEERING An (AlInGaN) based semiconductor device, comprising a first layer that is a semipolar or nonpolar nitride (AlInGaN) layer having a lattice constant that is partially or fully relaxed, deposited on a substrate or a template, wherein there are one or more dislocations at ... | 05/03/2012 |
| 20120080690 | Method for Manufacturing a Composite Wafer Having a Graphite Core, and Composite Wafer Having a Graphite Core According to an embodiment, a composite wafer includes a carrier substrate having a graphite core and a monocrystalline semiconductor layer attached to the carrier substrate.... | 04/05/2012 |
| 20120080753 | GALLIUM ARSENIDE BASED MATERIALS USED IN THIN FILM TRANSISTOR APPLICATIONS Embodiments of the invention provide a method of forming a group III-V material utilized in thin film transistor devices. In one embodiment, a gallium arsenide based (GaAs) layer with or without dopants formed from a solution based precursor may be utilized in thin film... | 04/05/2012 |
| 20120083100 | THERMALIZING GAS INJECTORS FOR GENERATING INCREASED PRECURSOR GAS, MATERIAL DEPOSITION SYSTEMS INCLUDING SUCH INJECTORS, AND RELATED METHODS Methods of depositing material on a substrate include forming a precursor gas and a byproduct from a source gas within a thermalizing gas injector. The byproduct may be reacted with a liquid reagent to form additional precursor gas, which may be injected from the therma... | 04/05/2012 |
| 20120083101 | SYSTEMS AND METHODS FOR FORMING SEMICONDUCTOR MATERIALS BY ATOMIC LAYER DEPOSITION Methods of depositing a III-V semiconductor material on a substrate include sequentially introducing a gaseous precursor of a group III element and a gaseous precursor of a group V element to the substrate by altering spatial positioning of the substrate with respect to... | 04/05/2012 |
| 20120081188 | WIDEBAND TEMPERATURE COMPENSATED RESONATOR AND WIDEBAND VCO A resonator of a VCO includes a fine tuning main varactor circuit, an auxiliary varactor circuit, and a coarse tuning capacitor bank circuit coupled in parallel with an inductance. The main varactor circuit includes a plurality of circuit portions that can be separately... | 04/05/2012 |
| 20120070967 | Method for Forming Gallium Nitride Devices with Conductive Regions Semiconductor structures comprising a III-nitride (e.g., gallium nitride) material region and methods associated with such structures are provided. In some embodiments, the structures include an electrically conductive material (e.g., gold) separated from certain other ... | 03/22/2012 |
| 20120068160 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME A semiconductor device according to an embodiment, includes a catalytic metal film, a graphene film, a contact plug, and an adjustment film. The catalytic metal film is formed above a substrate. The graphene film is formed on the catalytic metal film. The contact plug i... | 03/22/2012 |
| 20120068142 | RESISTANCE RANDOM ACCESS MEMORY ELEMENT AND METHOD FOR MAKING THE SAME A resistance random access memory element includes a first electrode, an insulating layer, a diffusing metal layer, and a second electrode superimposed in sequence. The insulating layer includes a plurality of pointed electrodes. A method for making a resistance random ... | 03/22/2012 |
| 20120070966 | METHOD FOR MANUFACTURING SEMICONDUCTOR ELEMENT A method for manufacturing a semiconductor element includes etching a surface of a substrate by a dry etching processing, performing a first heat treatment for the surface of the substrate in an atmosphere including halogen, and forming a nitride semiconductor on the su... | 03/22/2012 |
| 20120068189 | Method for Vertical and Lateral Control of III-N Polarity Disclosed herein is a method of: depositing a patterned mask layer on an N-polar GaN epitaxial layer of a sapphire, silicon, or silicon carbide substrate; depositing an AlN inversion layer on the open areas; removing any remaining mask; and depositing a III-N epitaxial ... | 03/22/2012 |
| 20120070964 | METHOD FOR ELIMINATING THE METAL CATALYST RESIDUES ON THE SURFACE OF WIRES PRODUCED BY CATALYTIC GROWTH This method for eliminating the catalyst residues present on the surface of solid structures made from a first material and obtained by catalytic growth, includes the following steps:
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| 20120070965 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME A semiconductor device includes a first conductive type first semiconductor region, a second semiconductor region, and a second conductive type lateral RESURF region. The first semiconductor region is arranged on a first electrode side. The second semiconductor region i... | 03/22/2012 |
| 20120068226 | Formation of Devices by Epitaxial Layer Overgrowth Methods and structures are provided for formation of devices on substrates including, e.g., lattice-mismatched materials, by the use of aspect ratio trapping and epitaxial layer overgrowth. A method includes forming an opening in a masking layer disposed over a substrat... | 03/22/2012 |
| 20120070919 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THEREOF, AND METHOD OF MANUFACTURING BASE MATERIAL It is an object of the invention to provide a lightweight semiconductor device having a highly reliable sealing structure which can prevent ingress of impurities such as moisture that deteriorate element characteristics, and a method of manufacturing thereof. A protecti... | 03/22/2012 |
| 20120068223 | BIDIRECTIONAL PROTECTION COMPONENT A bidirectional protection component formed in a semiconductor substrate of a first conductivity type including a first implanted area of the first conductivity type, an epitaxial layer of the second conductivity type on the substrate and the first implanted area, a sec... | 03/22/2012 |
| 20120068193 | STRUCTURE AND METHOD FOR INCREASING STRAIN IN A DEVICE A method and structure are disclosed for increasing strain in a device, specifically an n-type field effect transistor (NFET) complementary metal-oxide-semiconductor (CMOS) device. Embodiments of this invention include growing an epitaxial layer, performing a cold carbo... | 03/22/2012 |
| 20120068285 | MAGNETORESISTIVE EFFECT ELEMENT, MAGNETIC MEMORY, AND METHOD OF MANUFACTURING MAGNETORESISTIVE EFFECT ELEMENT According to one embodiment, a magnetoresistive effect element includes a first magnetic layer including perpendicular anisotropy to a film surface and an invariable magnetization direction, the first magnetic layer having a magnetic film including an element selected f... | 03/22/2012 |
| 20120068224 | METHOD OF PRODUCING SEMICONDUCTOR WAFER, AND SEMICONDUCTOR WAFER A method of producing a semiconductor wafer suited to form types of devices such as HBT and FET on a single semiconductor wafer is provided. The method, by repeating steps including introducing, into a reaction chamber for forming a semiconductor by crystal growth, a fi... | 03/22/2012 |
| 20120070929 | METHOD FOR FABRICATING WAFER PRODUCT AND METHOD FOR FABRICATING GALLIUM NITRIDE BASED SEMICONDUCTOR OPTICAL DEVICE Provided is a method for fabricating a wafer product including an active layer grown on a gallium oxide substrate and allowing an improvement in emission intensity. In step S105, a buffer layer 13 comprised of a Group III nitride such as GaN, AlGaN, or AlN... | 03/22/2012 |
