Did You Know...
...that to encourage use of his new invention, the shopping cart, market owner Sylvan Goldman hired fake shoppers to push the carts around his store in Oklahoma City? Seems his customers were reluctant to give up their hand-carried baskets.
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| Application No. | Application Title | Issue Date |
| 20120104633 | ELECTRONIC DEVICE AND ELECTRONIC APPARATUS An electronic device includes a semiconductor device and a wiring substrate having a wiring pattern. The semiconductor device includes: a semiconductor chip having an electrode; a convex-shaped resin protrusion provided on a surface of the semiconductor chip, the surfac... | 05/03/2012 |
| 20120104604 | CRACK ARREST VIAS FOR IC DEVICES An integrated circuit (IC) device includes a substrate having a top surface including active circuitry including a plurality of I/O nodes, and a plurality of die pads coupled to the plurality of I/O nodes. A first dielectric layer including first dielectric vias is over... | 05/03/2012 |
| 20120104632 | PROCESS FOR FABRICATING AN INTEGRATED CIRCUIT COMPRISING AN ANALOG BLOCK AND A DIGITAL BLOCK, AND CORRESPONDING INTEGRATED CIRCUIT The integrated circuit comprises an analog block and a digital block in and/or on the same substrate. At least part of a first integrated-circuit portion (BA2) corresponding to the analog block is produced in a native technology and a second integrated-circuit po... | 05/03/2012 |
| 20120104634 | CHIP PACKAGE STRUCTURE AND MANUFACTURING METHODS THEREOF A chip package structure includes a chip module, a plurality of pre-patterned structures, a filling material layer, and a redistribution layer. The chip module includes a chip including an upper surface, a side surface, and an active surface. The pre-patterned structure... | 05/03/2012 |
| 20120049389 | BOND PAD FOR SEMICONDUCTOR DIE A semiconductor die has rows of bond pads along the edges of a major surface. The corners of the die are designated as keep out areas, with design layout rules prohibiting a probe-able bond pad from being placed in the keep out areas so that a minimum distance may be ma... | 03/01/2012 |
| 20120049351 | PACKAGE SUBSTRATE AND FLIP CHIP PACKAGE INCLUDING THE SAME A package substrate includes an insulating substrate, a functional pattern and a main dummy pattern. A semiconductor chip is arranged on the insulating substrate. The functional pattern is formed on the insulating substrate. The functional pattern is electrically connec... | 03/01/2012 |
| 20120043673 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE Provided are three-dimensional semiconductor devices. A device includes an electrode structure including conductive patterns sequentially stacked on a substrate, a semiconductor pattern penetrating the electrode structure and including channel regions adjacent to the co... | 02/23/2012 |
| 20120032325 | SEMICONDUCTOR DEVICE There is provided a semiconductor device with which stress can be prevented from locally concentrating on an external connecting terminal on a post and thus damages of the external connecting terminal can be prevented. The semiconductor device includes a semiconductor c... | 02/09/2012 |
| 20120025403 | DESIGN APPARATUS OF SEMICONDUCTOR DEVICE, DESIGN METHOD OF SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE A design method of a semiconductor device includes four steps. The first step is of arranging grid wiring which includes a plurality of wiring lines arranged in parallel to each other and a plurality of vias connecting the plurality of wiring lines with each other. The ... | 02/02/2012 |
| 20120025402 | METHODS OF FORMING SEMICONDUCTOR DEVICE STRUCTURES AND SEMICONDUCTOR DEVICE STRUCTURES INCLUDING A UNIFORM PATTERN OF CONDUCTIVE LINES Methods of forming semiconductor device structures are disclosed. One method comprises forming a plurality of loops of a conductive material. Each loop of the plurality of loops comprises a uniform pattern. In one embodiment, a portion of the conductive material is remo... | 02/02/2012 |
| 20110316174 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE In a semiconductor integrated circuit device, arrangement relationship of power source area I/O pads differs between a peripheral portion and a center portion of a gate region of a chip. That is, in two columns and two rows of the peripheral portion of the gate region, ... | 12/29/2011 |
| 20110309515 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD FOR DESIGNING THE SAME A semiconductor integrated circuit device includes a semiconductor chip including input/output cells, pads formed on a surface of the semiconductor chip, and interconnects formed on the surface of the semiconductor chip to electrically connect at least some of the plura... | 12/22/2011 |
| 20110304060 | METAL THIN FILM CONNECTION STRUCTURE, MANUFACTURING METHOD THEREOF AND ARRAY SUBSTRATE Embodiments of the invention relates to a metal thin film connection structure, comprising a first metal layer pattern; a second metal layer pattern which is separately disposed with the first metal layer pattern; a first insulating layer formed on the first metal layer... | 12/15/2011 |
| 20110304061 | SEMICONDUCTOR DEVICE A semiconductor device in which it is possible to suppress short-circuiting between pads for chip arising from dicing processing is provided. The semiconductor device includes a semiconductor substrate, multiple first pads, and multiple second pads. The first pads are f... | 12/15/2011 |
| 20110291274 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE A method of manufacturing a semiconductor device is disclosed. One embodiment provides a carrier. Semiconductor chips are placed over the carrier. The semiconductor chips include contact elements. A polymer material is applied over the semiconductor chips and the carrie... | 12/01/2011 |
| 20110295543 | PERFORMANCE IMPROVEMENT FOR A MULTI-CHIP SYSTEM VIA KERF AREA INTERCONNECT A semiconductor wafer comprises a first chip and a second chip, each chip comprising a core, link layer and physical layer. A kerf area physically connects the two chips on the wafer, and a kerf area interconnect selectively couples the link layers of the two chips whil... | 12/01/2011 |
| 20110285034 | ELECTRICAL CONNECTIONS FOR MULTICHIP MODULES Conductive lines are formed on a wafer containing multiple circuits. The conductive lines are isolated from the circuits formed within the wafer. Chips are mounted on the wafer and have their chip pads connected to the conductive lines of the wafer. The wafer may then b... | 11/24/2011 |
| 20110278743 | LAYOUT STRUCTURE AND VERSION CONTROL CIRCUIT FOR INTEGRATED CIRCUITS The present invention relates to a layout structure and a version control circuit for integrated circuits. The layout structure for integrated circuits according to the present invention comprises a signal-supplying unit and at least a transfer cell. The signal-supplyin... | 11/17/2011 |
| 20110247690 | SEMICONDUCTOR DEVICES COMPRISING ANTIREFLECTIVE CONDUCTIVE LAYERS AND METHODS OF MAKING AND USING A semiconductor device includes a semiconductor substrate and an antireflective conductive layer. The antireflective conductive layer includes a metal layer disposed on the semiconductor substrate and defining at least one array of apertures through the metal layer. Eac... | 10/13/2011 |
| 20110241225 | SEMICONDUCTOR MEMORY DEVICE A semiconductor memory device includes a memory block having a three-dimensional memory cell array structure in which memory cell arrays are stacked, the memory cell array including: a plurality of first interconnections which are parallel to one another; a plurality of... | 10/06/2011 |
| 20110233796 | Semiconductor Devices and Electronic Systems A semiconductor device and an electronic system are provided. The semiconductor device includes a lower conductive pattern, and an intermediate conductive pattern on the lower conductive pattern. An upper conductive pattern is provided on the intermediate conductive pat... | 09/29/2011 |
| 20110221076 | SEMICONDUCTOR DEVICE A semiconductor device according to the present invention includes: a power semiconductor element that is a semiconductor element; bonding parts provided for bonding of an upper surface and a lower surface of the semiconductor element; and metal plates bonded to the pow... | 09/15/2011 |
| 20110213907 | SEMICONDUCTOR RESISTANCE ELEMENT, SEMICONDUCTOR MODULE INCLUDING THE SAME, AND PROCESSOR-BASED SYSTEM INCLUDING THE SEMICONDUCTOR MODULE Provided may be a semiconductor resistance element including resistance patterns disposed on an insulating substrate. The substrate may have first and second planer surfaces disposed in a first direction, third and fourth planar surfaces at least between the first and s... | 09/01/2011 |
| 20110198761 | Methods for Multi-Wire Routing and Apparatus Implementing Same A rectangular interlevel connector array (RICA) is defined in a semiconductor chip. To define the RICA, a virtual grid for interlevel connector placement is defined to include a first set of parallel virtual lines that extend across the layout in a first direction, and ... | 08/18/2011 |
| 20110187008 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTER DEVICE A semiconductor device has a semiconductor chip and a first interconnection tape. The semiconductor chip has a plurality of first electrode pads arranged on a first surface. The first interconnection tape is in contact with each of the plurality of first electrode pads ... | 08/04/2011 |
| 20110180942 | INTERCONNECTION STRUCTURE An interconnection structure includes: first and second differential signal interconnections provided to transmit a differential signal; and first and second voltage interconnections applied with predetermined voltages. The first voltage interconnection, the first diffe... | 07/28/2011 |
| 20110180941 | THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME Provided is a three-dimensional semiconductor device and method for fabricating the same. The device includes a first electrode structure and a second electrode structure stacked sequentially on a substrate. The first and second electrode structures include stacked firs... | 07/28/2011 |
| 20110168999 | Semiconductor wire grid, display apparatus having the same, and method of manufacturing the display apparatus A semiconductor wire grid may include a plurality of wires arranged separately on a substrate, formed of a semiconductor, and including a groove therebetween, wherein conductivity of the semiconductor wire grid varies according to an applied voltage such that a polariza... | 07/14/2011 |
| 20110156282 | Gate Conductor Structure A gate conductor structure is provided having a barrier region between a N-type device and a P-type device, wherein the barrier region minimizes or eliminates cross-diffusion of dopant species across the barrier region. The barrier region comprises at least one sublitho... | 06/30/2011 |
| 20110140288 | Systems and Methods Employing a Physically Asymmetric Semiconductor Device Having Symmetrical Electrical Behavior An integrated circuit device comprising a first elongate structure and a second elongate structure arranged parallel to each other and defining a space therebetween. The integrated circuit device also includes conductive structures distributed in the space between the f... | 06/16/2011 |
| 20110140287 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH BOND WIRE PADS AND METHOD OF MANUFACTURE THEREOF A method of manufacture of an integrated circuit packaging system includes: forming a device over a substrate including a bond wire pad row located between a perimeter of the substrate and the device; configuring the bond wire pad row to include three sided bond wire pa... | 06/16/2011 |
| 20110133184 | SEMICONDUCTOR DEVICE A semiconductor device includes an insulating film formed on a substrate; an interconnect layer including a plurality of interconnects formed in the insulating film; and a pad formed on the insulating film. In a region containing at least a part of a section below the p... | 06/09/2011 |
| 20110127681 | CHIP PACKAGE AND FABRICATION METHOD THEREOF A chip package and a fabrication method thereof are provided according to an embodiment of the invention. The chip package includes a semiconductor substrate containing a chip and having a device area and a peripheral bonding pad area. A plurality of conductive pads is ... | 06/02/2011 |
| 20110121467 | SEMICONDUCTOR DEVICE METAL PROGRAMMABLE POOLING AND DIES A pool of die designs includes die designs having metal programmable base layers. Die designs from the pool are selected for use in fabricating dies. Die designs are added to the pool by customization of die designs already in the pool or by preparing custom die designs... | 05/26/2011 |
| 20110108982 | PRINTED CIRCUIT BOARD A printed circuit board includes a body part formed with connection pads on a first surface thereof; and a warpage compensating part formed over the first surface of the body part and having a height that increases from edges toward a center of the warpage compensating ... | 05/12/2011 |
| 20110101545 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH BOND PAD AND METHOD OF MANUFACTURE THEREOF A method of manufacture of an integrated circuit packaging system includes: providing a semiconductor substrate; forming a core region on the semiconductor substrate with the core region having a core side; forming an inner bond pad on the semiconductor substrate with t... | 05/05/2011 |
| 20110089579 | MULTI-CHIP MODULE A multi-chip module includes: a board; a wiring board disposed on the board and including a wiring pattern; and a plurality of chips disposed on the wiring board. Each of the plurality of chips is connected with at least one of the other chips, and the plurality of chip... | 04/21/2011 |
| 20110089575 | MULTICHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME A semiconductor package includes at least one semiconductor chip mounted to a circuit board and separated from the circuit board by a predetermined distance. A support located between the circuit board and the first semiconductor chip supports the first semiconductor ch... | 04/21/2011 |
| 20110084410 | Wiring Substrate for a Semiconductor Chip, and Semiconducotor Package Having the Wiring Substrate A wiring substrate for a semiconductor chip includes a substrate, first and second wiring layers and a plurality of first and second bonding pads. The substrate has a first surface and a second surface opposite to the first surface, a window extending from the first sur... | 04/14/2011 |
| 20110084365 | Through Silicon Via (TSV) Wire Bond Architecture A through silicon via architecture for integrated circuits is provided. The integrated circuit (IC) includes a substrate with a top surface and a bottom surface with circuitry formed on the top surface, a plurality of bonding pads formed along a periphery of the bottom ... | 04/14/2011 |
