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| Application No. | Application Title | Issue Date |
| 20120126411 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF A semiconductor device of the present invention has a purpose to form a structure of preventing outflow of solder at low costs. A semiconductor element is bonded to a substrate through a solder layer. An outflow-preventing part is provided to surround the solder layer t... | 05/24/2012 |
| 20120104618 | LOW TEMPERATURE BONDING MATERIAL AND BONDING METHOD A bonding material comprising metal particles coated with an organic substance having carbon atoms of 2 to 8, wherein the metal particles comprises first portion of 100 nm or less, and a second portion larger than 100 nm but not larger than 100 μm, each of the portions... | 05/03/2012 |
| 20120106117 | ULTRA-THIN INTERPOSER ASSEMBLIES WITH THROUGH VIAS A 3D interconnect structure comprising an ultra-thin interposer having a plurality of ultra-high density of through-via interconnections defined therein. The 3D interposer electrically connects first and second electronic devices in vertical dimension and has the same o... | 05/03/2012 |
| 20120080799 | Semiconductor Module Comprising an Insert and Method for Producing a Semiconductor Module Comprising an Insert A power semiconductor module is fabricated by providing a base with a metal surface and an insulating substrate comprising an insulation carrier having a bottom side provided with a bottom metallization layer. An insert exhibiting a wavy structure is provided. The inser... | 04/05/2012 |
| 20120032335 | ELECTRONIC COMPONENT AND METHOD FOR MANUFACTURING THE SAME An electronic component including a wiring board having a power-source pattern and a signal pattern, a semiconductor element mounted on the wiring board and having a power-source electrode pad and a signal electrode pad, a first connection portion being made of a conduc... | 02/09/2012 |
| 20120025373 | Semiconductor Device and Method of Forming Vertically Offset Bond on Trace Interconnects on Different Height Traces A method of making a semiconductor device includes providing a substrate, and forming a first conductive layer over the substrate. A patterned layer is formed over the first conductive layer. A second conductive layer is formed in the patterned layer. A height of the se... | 02/02/2012 |
| 20120018890 | SEMICONDUCTOR DEVICE A semiconductor device of the present invention includes a supporting board, an electrode surface processing layer formed on the supporting board, a semiconductor element, and a solder material containing a first metal composed mainly of bismuth and a second metal havin... | 01/26/2012 |
| 20120007247 | Resin-Encapsulated Semiconductor Device A resin-sealed semiconductor device includes a semiconductor chip including a silicon substrate; a die pad on which the semiconductor chip is secured via a solder layer; a sealing resin layer sealing the semiconductor chip; and lead terminals connected electrically with... | 01/12/2012 |
| 20110316117 | DIE PACKAGE AND A METHOD FOR MANUFACTURING THE DIE PACKAGE A die package and a method for manufacturing the die package are provided. The die package includes a second die arranged above a first die, the first die comprising an interconnect region on a surface facing the second die, wherein the second die is arranged laterally ... | 12/29/2011 |
| 20110304051 | THERMAL INTERFACE MATERIAL WITH SUPPORT STRUCTURE Various semiconductor chip thermal interface material methods and apparatus are disclosed. In one aspect, a method of establishing thermal contact between a first semiconductor chip and a heat spreader is provided. The method includes placing a thermal interface materia... | 12/15/2011 |
| 20110291282 | JUNCTION BODY, SEMICONDUCTOR MODULE, AND MANUFACTURING METHOD FOR JUNCTION BODY A junction body has a first member and a second member each of which is provided with a joining surface whose main component is copper. A solder member containing, in a tin-base solder material, a three-dimensional web structure whose main component is copper is provide... | 12/01/2011 |
| 20110293962 | SOLDER JOINTS WITH ENHANCED ELECTROMIGRATION RESISTANCE Electronic assemblies and solders used in electronic assemblies are described. One embodiment includes a die and a substrate, with a solder material positioned between the die and the substrate, the solder comprising at least 91 weight percent Sn, 0.4 to 1.0 weight perc... | 12/01/2011 |
| 20110227228 | FILLING COMPOSITION, SEMICONDUCTOR DEVICE INCLUDING THE SAME, AND METHOD OF FABRICATING THE SEMICONDUCTOR DEVICE Provided is a filling composition. The filling composition includes: a first particle including Cu and/or Ag; a second particle electrically connecting the first particles; and a resin containing a high molecular compound, a hardener, and a reducer, in which the first a... | 09/22/2011 |
| 20110180929 | GOLD-TIN-INDIUM SOLDER FOR PROCESSING COMPATIBILITY WITH LEAD-FREE TIN-BASED SOLDER Disclosed in this specification is a lead-free soldering alloy made of gold, tin and indium. The tin is present in a concentration of 17.5% to 20.5%, the indium is present in a concentration of 2.0% to 6.0% and the balance is gold and the alloy has a melting point betwe... | 07/28/2011 |
| 20110127669 | SOLDER STRUCTURE, METHOD FOR FORMING THE SOLDER STRUCTURE, AND SEMICONDUCTOR MODULE INCLUDING THE SOLDER STRUCTURE The invention provides a solder structure which is least likely to develop Sn whiskers and a method for forming such a solder structure. The solder structure includes an Sn alloy capable of a solid-liquid coexistent state and an Au (or Au alloy) coating covering at leas... | 06/02/2011 |
| 20110115084 | LEAD-FREE SOLDER CONNECTION STRUCTURE AND SOLDER BALL Solder used for flip chip bonding inside a semiconductor package was a Sn—Pb solder such as a Pb-5Sn composition. Lead-free solders which have been studied are hard and easily form intermetallic compounds with Sn, so they were not suitable for a flip chip connection s... | 05/19/2011 |
| 20110101533 | INTEGRATED (MULTILAYER) CIRCUITS AND PROCESS OF PRODUCING THE SAME A process of forming a semiconductor integrated circuit that includes the steps of: forming at least a first element having a first pattern of conductive material and including a polymer layer surrounding the conductive material, forming at least a second element having... | 05/05/2011 |
| 20110089567 | Production Method and Production Apparatus of Tin or Solder Alloy for Electronic Components, and Solder Alloy The invention provides a technique and a device that dramatically improve joint reliability of miniature joints of fine electronic components. According to the invention, when producing a tin or a solder alloy used for electronic components, an ingot of a tin or a solde... | 04/21/2011 |
| 20110089568 | POWER SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR A power semiconductor device includes a substrate, an element circuit pattern formed on the substrate and made of Cu covered with an electroless Ni—P plating layer, and a power semiconductor element bonded to the element circuit pattern by a solder, wherein the solder... | 04/21/2011 |
| 20110079911 | Method for the Connection of Two Wafers, and a Wafer Arrangement A method for the connection of two wafers in which a contact area is formed between the two wafers by placing the two wafers one on top of the other. The contact area is heated locally and for a limited time. A wafer arrangement comprises two wafers which have been plac... | 04/07/2011 |
| 20110042817 | SOLDER JOINT STRUCTURE, AND JOINING METHOD OF THE SAME A layer (105) of a metal having a crystal lattice different from the crystal lattice of a joining material (106) mainly containing Bi is placed on a surface (102b) of a semiconductor device (102), and a layer (104) of an element... | 02/24/2011 |
| 20110012263 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME In order to achieve the highly reliable and highly functional semiconductor device capable of the high-speed transmission by stacking thin chips and substrates, a connecting process and a connecting structure capable of making a solid connection at a low temperature wit... | 01/20/2011 |
| 20100308465 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME There is provided a semiconductor device including: a circuit board formed by bonding a first and a second metal plates to both surfaces of an insulating substrate respectively, at least one semiconductor element to be bonded to an external surface of the first metal pl... | 12/09/2010 |
| 20100289148 | SEMICONDUCTOR POWER MODULE Use of Pb-free solder has become essential due to the environmental problem. A power module is formed by soldering substrates with large areas. It is known that in Sn-3Ag-0.5Cu which hardly creeps and deforms with respect to large deformation followed by warpage of the ... | 11/18/2010 |
| 20100276808 | SURFACE MOUNTING ELECTRONIC COMPONENT AND MANUFACTURING METHOD THEREOF The electric component includes at least a set of electrode terminals 2, 3, a semiconductor element 4 electrically connected with the set of electrode terminals, and a package 6 made of synthetic resin and sealing the electrode terminals and the sem... | 11/04/2010 |
| 20100193801 | SOLDER MATERIAL, METHOD FOR MANUFACTURING THE SAME, JOINED BODY, METHOD FOR MANUFACTURING THE SAME, POWER SEMICONDUCTOR MODULE, AND METHOD FOR MANUFACTURING THE SAME A zinc based solder material 55 of the present invention is prepared by providing on the surface of a zinc based material 50, from which an oxide film 501 has been removed or at which an oxide film 501 does not exist, with a coating layer ... | 08/05/2010 |
| 20100164104 | Structures and Methods for Improving Solder Bump Connections in Semiconductor Devices Structures with improved solder bump connections and methods of fabricating such structures are provided herein. The method includes forming an upper wiring layer in a dielectric layer and depositing one or more dielectric layers on the upper wiring layer. The method fu... | 07/01/2010 |
| 20100148367 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME A semiconductor device includes a die pad having a surface on which a first solder bonding layer is formed, and made of metal; and a semiconductor element fixed on the first solder bonding layer on the die pad by a solder material made mostly of bismuth. The first solde... | 06/17/2010 |
| 20100001400 | SOLDER CONTACT A low melting temperature solder is provided for producing a solder contact between a connection element and a contact structure of a semiconductor component.... | 01/07/2010 |
| 20090294962 | PACKAGING SUBSTRATE AND METHOD FOR FABRICATING THE SAME A packaging substrate and a method for fabricating the same are proposed, including: providing a substrate body having a first surface and an opposing second surface, wherein the first surface has a plurality of flip-chip solder pads and wire bonding pads and the second... | 12/03/2009 |
| 20090294974 | BONDING METHOD FOR THROUGH-SILICON-VIA BASED 3D WAFER STACKING There is described a bonding method for through-silicon-via bonding of a wafer stack in which the wafers are formed with through-silicon-vias and lateral microchannels that are filled with solder. To fill the vias and channels the wafer stack is placed in a soldering ch... | 12/03/2009 |
| 20090166876 | SEMICONDUCTOR DEVICE AND DIE BONDING MATERIAL In a semiconductor device bonded to a motherboard with a bonding material having a melting point of 200° C. to 230° C., a bonding material 15 which is a die bonding material for bonding a semiconductor element 13 to a semiconductor substrate 11 is... | 07/02/2009 |
| 20090146301 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME A semiconductor device capable of realizing highly reliable three-dimensional mounting, and a method of manufacturing the same, are provided. A projected electrode 9 is formed in a region outside of an element mounting region of a substrate 5. The projecte... | 06/11/2009 |
| 20090085216 | Semiconductor device The present invention provides a semiconductor device excellent in the reliability of connection between the semiconductor device and a mounting board. The semiconductor device has external connecting terminals. Each of the external connecting terminals includes a Cu el... | 04/02/2009 |
| 20090065943 | Microelectronic Assembly Having Second Level Interconnects Including Solder Joints Reinforced with Crack Arrester Elements and Method of Forming Same A microelectronic assembly and a method of forming the assembly. The microelectronic assembly includes a package having a package substrate having a die side and a carrier side, and substrate lands on the carrier side thereof; a microelectronic die mounted on the packag... | 03/12/2009 |
| 20080315427 | SUBSTRATE BONDING METHOD AND SEMICONDUCTOR DEVICE (a) A first Sn absorption layer (5) is formed on the principal surface of a first substrate (1), the first Sn absorption layer being made of metal absorbing Sn from AuSn alloy and lowering a relative proportion of Sn in the AuSn alloy. (b) A second Sn abso... | 12/25/2008 |
| 20080303163 | THROUGH SILICON VIA DIES AND PACKAGES A method for preparing a die for packaging is disclosed. A die having first and second major surfaces is provided. Vias and a mask layer are formed on the first major surface of the die. The mask includes mask openings that expose the vias. The mask openings are filled ... | 12/11/2008 |
| 20080290502 | INTEGRATED CIRCUIT PACKAGE WITH SOLDERED LID FOR IMPROVED THERMAL PERFORMANCE An integrated circuit die includes a circuit surface and a back surface opposite the circuit surface. An underbump metallurgy is formed on a back surface. A layer of solder is formed on the underbump metallurgy.... | 11/27/2008 |
| 20080245846 | HEAT CYCLE-ABLE CONNECTION A method of creating an electrical connection involves providing a pair of contacts each on one of two different chips, the pair of contacts defining a volume therebetween, the volume containing at least two compositions each having melting points, the compositions havi... | 10/09/2008 |
| 20080191358 | SOLDER DEPOSITION ON WAFER BACKSIDE FOR THIN-DIE THERMAL INTERFACE MATERIAL A solder is deposited on the backside of a wafer. The wafer can be predeposited with a barrier layer such as a titanium base and other materials. Deposition is carried out by electroplating, electroless plating, chemical vapor deposition, and physical vapor deposition. ... | 08/14/2008 |
