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| Application No. | Application Title | Issue Date |
| 20120126407 | WAFER LEVEL CHIP PACKAGE AND A METHOD OF FABRICATING THEREOF Wafer level chip packages including risers having sloped sidewalls and methods of fabricating such chip packages are disclosed. The inventive wafer level chip packages may advantageously be used in various microelectronic assemblies.... | 05/24/2012 |
| 20120126406 | USING BUMP BONDING TO DISTRIBUTE CURRENT FLOW ON A SEMICONDUCTOR POWER DEVICE A semiconductor power chip may have a semiconductor die having a power device fabricated on a substrate thereof, wherein the power device has at least one first contact element, a plurality of second contact elements and a plurality of third contact elements arranged on... | 05/24/2012 |
| 20120104543 | HIGH-SPEED MEMORY SOCKETS AND INTERPOSERS High-speed memory systems that consume a reduced amount of board space, have a low height or profile, or both. This reduction in board space and height may result in shorter signal paths from a board to a memory device, thereby improving the high-speed performance of th... | 05/03/2012 |
| 20120104605 | Chip Design having Integrated Fuse and Method for the Production Thereof A chip design (1) comprising an external supply connection (VBAT), an internal supply connection (VDD), an integrated circuit (2) that is coupled to the internal supply connection (VDD) for voltage supply, and a fuse (3) that electrically connects t... | 05/03/2012 |
| 20120104607 | STACKED SEMICONDUCTOR PACKAGES AND RELATED METHODS The present stacked semiconductor packages include a bottom package and a top package. The bottom package includes a substrate, a solder mask layer, a plurality of conductive pillars and a die electrically connected to the substrate. The solder mask layer has a pluralit... | 05/03/2012 |
| 20120104604 | CRACK ARREST VIAS FOR IC DEVICES An integrated circuit (IC) device includes a substrate having a top surface including active circuitry including a plurality of I/O nodes, and a plurality of die pads coupled to the plurality of I/O nodes. A first dielectric layer including first dielectric vias is over... | 05/03/2012 |
| 20120104608 | WAFER LEVEL PACKAGE HAVING A STRESS RELIEF SPACER AND MANUFACTURING METHOD THEREOF In a semiconductor device package having a stress relief spacer, and a manufacturing method thereof, metal interconnect fingers extend from the body of a chip provide for chip interconnection. The metal fingers are isolated from the body of the chip by a stress-relief s... | 05/03/2012 |
| 20120104606 | BALL GRID ARRAY SEMICONDUCTOR DEVICE AND ITS MANUFACTURE A semiconductor device includes: stacked semiconductor chips having respective input/output pads on surfaces thereof; a lower resin body molding the lower semiconductor chip and having a surface coplanar with the lower chip; an upper resin body molding the upper chip an... | 05/03/2012 |
| 20120068338 | IMPEDANCE CONTROLLED PACKAGES WITH METAL SHEET OR 2-LAYER RDL A microelectronic assembly is disclosed that is capable of achieving a desired impedance for raised conductive elements. The microelectronic assembly may include an interconnection element, a surface conductive element, a microelectronic device, a plurality of raised co... | 03/22/2012 |
| 20120068339 | VLSI Package for High Performance Integrated Circuit A packaged integrated circuit is presented for placement on a printed circuit board (PCB) layer providing power lines and data access channels. The packaged integrated circuit includes; a package substrate having data channels and power lines; a circuit substrate having... | 03/22/2012 |
| 20120068341 | Method for Depackaging Prepackaged Integrated Circuit Die and a Product from the Method A method for providing a known good integrated circuit die having enhanced planarity from a prepackaged integrated circuit die having a surface warpage such as in a ball grid array (BGA) package is provided. A partially-depackaged integrated circuit package is affixed t... | 03/22/2012 |
| 20120068340 | Ball grid array semiconductor package and method of manufacturing the same Provided is a BGA semiconductor package including: a substrate on which a semiconductor device is mounted; an adhesive for adhering the semiconductor device and the substrate to each other; a micro ball having conductivity, the micro ball being fitted into a through-hol... | 03/22/2012 |
| 20120049361 | SEMICONDUCTOR INTEGRATED CIRCUIT A semiconductor integrated circuit includes a semiconductor chip including a memory cell array, a plurality of first through-chip vias configured to vertically penetrate through the semiconductor chip and operate as an interface for a signal and a supply voltage, and a ... | 03/01/2012 |
| 20120049363 | PACKAGE STRUCTURE A package structure is provided, which includes a dielectric layer having opposing first and second surfaces, and through holes penetrating the surfaces; a strengthening layer formed on the first surface; a circuit layer formed on the second surface, and having wire bon... | 03/01/2012 |
| 20120049364 | EMEBEDDED STRUCTURES AND METHODS OF MANUFACTURE THEREOF Embodiments of the present disclosure provide a method that comprises providing a first die having a surface comprising a bond pad to route electrical signals of the first die and attaching the first die to a layer of a substrate. The method further comprises forming on... | 03/01/2012 |
| 20120049359 | BALL GRID ARRAY PACKAGE A BGA package comprises a substrate, a chip disposed on the substrate, and a plurality of solder balls disposed under the substrate. The substrate further has a plurality of ball pads and a solder mask having a plurality of openings to expose the ball pads where the bal... | 03/01/2012 |
| 20120049365 | SEMICONDUCTOR PACKAGE A semiconductor package is provided. The semiconductor package includes a package substrate, a plurality of semiconductor chips, and a plurality of connection terminals. The package substrate includes a center portion, which has a first recess with a portion of a top of... | 03/01/2012 |
| 20120049366 | PACKAGE STRUCTURE HAVING THROUGH-SILICON-VIA (TSV) CHIP EMBEDDED THEREIN AND FABRICATION METHOD THEREOF A package structure includes a dielectric layer having a first surface and a second surface; a through-silicon-via (TSV) chip embedded in the dielectric layer, wherein the TSV chip has a plurality of conductive TSVs, and electrode pads formed on a surface of the TSV chi... | 03/01/2012 |
| 20120049358 | Semiconductor Device and Semiconductor Process for Making the Same The present invention relates to a semiconductor device and a semiconductor process for making the same. The semiconductor device of the present invention includes a semiconductor substrate, at least one conductive via and at least one insulation ring. The semiconductor... | 03/01/2012 |
| 20120049367 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE According to the embodiment, a pad electrode, a protective film, an under barrier metal film, and an electrode wiring portion are provided. The pad electrode is formed on a semiconductor substrate. The protective film is formed on the semiconductor substrate so that a s... | 03/01/2012 |
| 20120049362 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THEREOF A semiconductor device has a first semiconductor chip 10 molded with a resin 12, a first metal 14 provided in the resin 12 in a circumference of the first semiconductor chip 10, and being exposed on a lower surface of the resin 12 | 03/01/2012 |
| 20120049360 | Semiconductor Package And Method For Making The Same The present invention relates to a semiconductor package and a method for making the same. The semiconductor package includes at least one first layer chip, a plurality of first metal bumps, at least one second layer chip and a package body. The first layer chip include... | 03/01/2012 |
| 20120043656 | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, AND MANUFACTURING METHOD OF SEMICONDUCTOR MODULE An improvement is achieved in the mounting reliability of a semiconductor device. A semiconductor chip is mounted over an upper surface of a wiring substrate. A plurality of solder balls are disposed individually over a plurality of lands formed on a lower surface of th... | 02/23/2012 |
| 20120043655 | WAFER-LEVEL PACKAGE USING STUD BUMP COATED WITH SOLDER A method of fabricated a wafer level package is described. In one embodiment, the method includes fabricating at least one active device on a semiconductor wafer that has not been singulated, with the active device having a plurality of bonding pads exposed at an upper ... | 02/23/2012 |
| 20120038045 | Stacked Semiconductor Device And Method Of Fabricating The Same A stacked semiconductor device may have a plurality of chips stacked in three-dimension. The stacked semiconductor device may include a first semiconductor chip and at least one second semiconductor chip. The first semiconductor chip may include a plurality of first thr... | 02/16/2012 |
| 20120038044 | CHIP SCALE PACKAGE AND FABRICATION METHOD THEREOF A CSP includes: a hard board having a first wiring layer with conductive pads; a plurality of conductive elements disposed on at least a portion of the conductive pads; an electronic component having opposite active and inactive surfaces and being mounted on the hard bo... | 02/16/2012 |
| 20120032167 | SEMICONDUCTOR PACKAGE AND METHOD OF TESTING SAME A packaged integrated circuit includes a substrate having a wire layout pattern and a solder mask layer. An integrated circuit attached to a surface of the substrate is electrically connected to the wire layout pattern. An encapsulation material covers at least the inte... | 02/09/2012 |
| 20120032328 | Package structure with underfilling material and packaging method thereof A method for packaging semiconductor device is provided, which comprises: providing a carrier substrate having a top surface and a back surface, a circuit arrangement on the top surface of the carrier substrate, and a through hole is disposed near the center of the carr... | 02/09/2012 |
| 20120032329 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE In semiconductor integrated circuit devices for vehicle use, an aluminum pad on a semiconductor chip and an external device are coupled to each other by wire bonding using a gold wire for the convenience of mounting. Such a semiconductor integrated circuit device, howev... | 02/09/2012 |
| 20120032327 | SYSTEMS AND METHODS FOR REINFORCING CHIP PACKAGES In accordance with some embodiments of the present disclosure, a chip package is provided. The chip package may include a chip, a substrate, and an interconnect layer disposed between the chip and the substrate. In some embodiments, the interconnect layer may include an... | 02/09/2012 |
| 20120032326 | AIR THROUGH-SILICON VIA STRUCTURE A silicon substrate has a conductive via extending from a first surface of the silicon substrate through the silicon substrate to a second surface of the silicon substrate. A dielectric via extends from the second surface of the silicon substrate toward the first surfac... | 02/09/2012 |
| 20120032330 | MITIGATION OF PLATING STUB RESONANCE BY CONTROLLING SURFACE ROUGHNESS Plating stub resonance in a circuit board may be mitigated by increasing surface roughness of the plating stub conductor. Roughening the plating stub increases its resistance due to the skin effect at higher frequencies, which decreases the quality factor of the transmi... | 02/09/2012 |
| 20120032693 | Crack detection in a semiconductor die and package A method is provided in which an impedance is measured between a first of a plurality of seal ring contact pads and a ground contact pad coupled to a semiconductor substrate of a semiconductor device. The first impedance value is obtained from the measured impedance, an... | 02/09/2012 |
| 20120025376 | BALL GRID ARRAY PACKAGE A BGA package includes an IC die, a substrate, a plurality of solder balls, and a square contact pad. The portions of the contact pad capable of interfering with the IC die are removed to ensure the space between two of the contact pads is sufficient to avoid noise inte... | 02/02/2012 |
| 20120025377 | SEMICONDUCTOR DEVICE AND METHOD OF DESIGNING A WIRING OF A SEMICONDUCTOR DEVICE A semiconductor device has an LSI chip including a semiconductor substrate, an LSI core section provided at a center portion of the semiconductor substrate and serving as a multilayered wiring layer of the semiconductor substrate, a first rewiring layer provided adjacen... | 02/02/2012 |
| 20120025375 | ROUTABLE ARRAY METAL INTEGRATED CIRCUIT PACKAGE FABRICATED USING PARTIAL ETCHING PROCESS An integrated circuit assembly is fabricated on a metal substrate strip in an array format that has raised circuitry pattern formed by photolithographic and metal etching processes. The circuitry pattern is formed on one side of the metal substrate only. The raised circ... | 02/02/2012 |
| 20120018886 | INTEGRATED CIRCUIT PACKAGE WITH OPEN SUBSTRATE AND METHOD OF MANUFACTURING THEREOF A method of manufacturing an integrated circuit package includes: forming a substrate including: forming a core layer, and forming vias in the core layer; forming a conductive layer having a predetermined thickness on the core layer and having substantially twice the pr... | 01/26/2012 |
| 20120018885 | SEMICONDUCTOR APPARATUS HAVING THROUGH VIAS A semiconductor apparatus includes a base substrate and a logic chip disposed on the base substrate. The logic chip includes a memory control circuit, a first through silicon via, and a second through silicon via. The memory control circuit is disposed on a first surfac... | 01/26/2012 |
| 20120018887 | MICROELECTRONIC DEVICE PACKAGES, STACKED MICROELECTRONIC DEVICE PACKAGES, AND METHODS FOR MANUFACTURING MICROELECTRONIC DEVICES A stackable microelectronic package includes a first microelectronic die attached to and electrically connecting with a first substrate. A second microelectronic die is attached to the first die on one side, and to a second substrate on the other side. Electrical connec... | 01/26/2012 |
| 20120018884 | Semiconductor package structure and forming method thereof The present invention provides a semiconductor package structure, which includes a substrate having a top surface and a back surface, a plurality of first connecting points on the top surface and a plurality of second connecting points on the back surface; a chip having... | 01/26/2012 |
