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| Application No. | Application Title | Issue Date |
| 20120126387 | ENHANCED HEAT SPREADER FOR USE IN AN ELECTRONIC DEVICE AND METHOD OF MANUFACTURING THE SAME An electronic device includes an integrated circuit (IC) die attached to a substrate, and electrical conductors connecting the IC die to the substrate. The electronic device also includes a heat spreader located over the IC die and having a concaved portion located over... | 05/24/2012 |
| 20120126388 | STACKABLE SEMICONDUCTOR ASSEMBLY WITH BUMP/FLANGE HEAT SPREADER AND DUAL BUILD-UP CIRCUITRY A stackable semiconductor assembly includes a semiconductor device, a heat spreader, an adhesive, a plated through-hole, first build-up circuitry and second build-up circuitry. The heat spreader includes a bump and a flange. The bump defines a cavity. The semiconductor ... | 05/24/2012 |
| 20120126347 | PACKAGES AND METHODS FOR PACKAGING Packaged integrated devices and methods of forming the same are provided. In one embodiment, a packaged integrated device includes a package substrate, a package lid, and an integrated circuit or microelectromechanical systems (MEMS) device. The package lid is mounted t... | 05/24/2012 |
| 20120104590 | Semiconductor Device and Method of Forming Penetrable Film Encapsulant Around Semiconductor Die and Interconnect Structure A semiconductor device has a plurality of bumps formed over a carrier. A semiconductor die is mounted to the carrier between the bumps. A penetrable film encapsulant layer having a base layer, first adhesive layer, and second adhesive layer is placed over the semiconduc... | 05/03/2012 |
| 20120080783 | THIN FLIP CHIP PACKAGE STRUCTURE A thin flip chip package structure comprises a substrate, a chip and a heat dissipation paste, the substrate comprises an insulating layer and a trace layer. The insulating layer comprises a top surface, a bottom surface and a plurality of apertures formed at the bottom... | 04/05/2012 |
| 20120043629 | Surface Mount Silicon Condenser Microphone Package The present invention relates to a surface mount package for a silicon condenser microphone. The inventive package uses a limited number of components which simplifies manufacturing and lowers costs, and features a substrate which performs functions for which multiple c... | 02/23/2012 |
| 20120032319 | HIGH-VOLTAGE PACKAGED DEVICE Packaged devices and methods for making and using the same are described. The packaged devices contain one or more circuit components, such as a die, that is attached to a leadframe having a first lead, a second lead, and a third lead (although, higher lead counts may b... | 02/09/2012 |
| 20120025215 | SEMICONDUCTOR PACKAGE WITH HEAT DISSIPATING STRUCTURE A semiconductor package includes a substrate, a number of electrodes formed in the substrate, a heat dissipating member fixed on the substrate, and at least one semiconductor chip mounted on the heat dissipating member and electrically connected to the electrodes. The h... | 02/02/2012 |
| 20120018869 | MOLD DESIGN AND SEMICONDUCTOR PACKAGE A chip package includes a carrier having a first and a second major surface. The first major surface includes an active region surrounded by an inactive region. The chip package includes contact pads in the active region for mating with chip contacts of a chip. A suppor... | 01/26/2012 |
| 20120007195 | APPARATUS FOR INTEGRATED CIRCUIT PACKAGING Apparatuses are disclosed, such as those involving integrated circuit packaging. In one embodiment, a chip package includes: an encapsulation having a top surface and a bottom surface facing away from the top surface. The package further includes a leadframe including a... | 01/12/2012 |
| 20120007227 | HIGH DENSITY CHIP STACKED PACKAGE, PACKAGE-ON-PACKAGE AND METHOD OF FABRICATING THE SAME A semiconductor package including a protection layer, a plurality of semiconductor chips stacked on the protection layer, an inner encapsulant disposed on the protection layer to surround side surfaces of the semiconductor chips, and a terminal disposed to be buried in ... | 01/12/2012 |
| 20120001315 | SEMICONDUCTOR DEVICE A semiconductor package includes a print circuit part, a lower chip, an upper chip, a thermal conductivity part, and an encapsulation resin. The lower chip and the upper chip are mounted on the print circuit part through wire bonding connection. The thermal conductivity... | 01/05/2012 |
| 20120001314 | MULTI-CHIP PACKAGE WITH THERMAL FRAME AND METHOD OF ASSEMBLING A semiconductor device includes a substrate having a plurality of substrate bonding pads disposed on a bonding surface thereof. A plurality of semiconductor dice are stacked on the bonding surface of the substrate to form a die stack. Each die has a plurality of die bon... | 01/05/2012 |
| 20120001316 | Package for High Power Devices A semiconductor device package is formed of DBC in which thinned MOSgated and/or diode die are soldered to the bottom of an etched depression in the upper conductive layer. A via in the insulation layer of the DBC is filled with a conductive material to form a resistive... | 01/05/2012 |
| 20120001317 | POWER SEMICONDUCTOR MODULE HAVING LAYERED INSULATING SIDE WALLS A power semiconductor module includes at least two interconnected power semiconductor units having actuatable power semiconductors, a module housing in which the power semiconductor units are disposed and which has an electrically insulating side wall, and at least one ... | 01/05/2012 |
| 20110316138 | HIGH FREQUENCY FAST RECOVERY DIODE A high-frequency fast recovery diode that includes a diode chip set, solder lugs, lead wires, lead terminals, a silicone coating layer and a plastic package body. The diode chip set includes n-diode chips arranged in the same polarity order sequentially, a part of the n... | 12/29/2011 |
| 20110310585 | Power Semiconductor Device and Power Conversion Device A power semiconductor device includes a plurality of power semiconductor elements constituting upper and lower arms of an inverter circuit, a first sealing member sealing the plurality of power semiconductor elements, a positive electrode-side terminal and a negative el... | 12/22/2011 |
| 20110291256 | Method for Fabricating a Semiconductor Chip Package and Semiconductor Chip Package A semiconductor chip includes a contact pad on a main surface of the chip. An electrically conductive layer is applied onto the contact pad. The main surface of the semiconductor chip is covered with an insulating layer. An electrically conductive contact area is formed... | 12/01/2011 |
| 20110285005 | PACKAGE SYSTEMS HAVING INTERPOSERS A package system includes a first integrated circuit disposed over an interposer. The interposer includes at least one molding compound layer including a plurality of electrical connection structures through the at least one molding compound layer. A first interconnect ... | 11/24/2011 |
| 20110285007 | Semiconductor Device and Method of Forming Ultra Thin Multi-Die Face-to-Face WLCSP A semiconductor device has a first semiconductor die stacked over a second semiconductor die which is mounted to a temporary carrier. A plurality of bumps is formed over an active surface of the first semiconductor die around a perimeter of the second semiconductor die.... | 11/24/2011 |
| 20110266665 | PRESS-PACK MODULE WITH POWER OVERLAY INTERCONNECTION Systems and methods for utilizing power overlay (POL) technology and semiconductor press-pack technology to produce semiconductor packages with higher reliability and power density are provided. A POL structure may interconnect semiconductor devices within a semiconduct... | 11/03/2011 |
| 20110241192 | Wafer-Level Semiconductor Device Packages with Stacking Functionality Described herein are wafer-level semiconductor device packages with stacking functionality and related stacked package assemblies and methods. In one embodiment, a semiconductor device package includes a set of connecting elements disposed adjacent to a periphery of a s... | 10/06/2011 |
| 20110241195 | FORMING IN-SITU MICRO-FEATURE STRUCTURES WITH CORELESS PACKAGES Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, forming dielectric material surrounding the die, forming buildup layers in the dielectric ma... | 10/06/2011 |
| 20110233750 | Arrangement of Two Substrates having an SLID Bond and Method for Producing such an Arrangement An arrangement having a first and a second substrate is disclosed, wherein the two substrates are connected to one another by means of an SLID (Solid Liquid InterDiffusion) bond. The SLID bond exhibits a first metallic material and a second metallic material, wherein th... | 09/29/2011 |
| 20110233749 | SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF FABRICATING THE SAME A semiconductor device package and a method of fabricating the same are disclosed. The semiconductor device package includes a substrate, a first chip, a jumper chip, a plurality of first bonding wires and a plurality of second bonding wires. The substrate has a plurali... | 09/29/2011 |
| 20110233748 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERCONNECT AND METHOD OF MANUFACTURE THEREOF A method of manufacture of an integrated circuit packaging system includes: providing an interposer having an interposer first side and an interposer second side opposing the interposer first side; mounting an integrated circuit to the interposer first side, the integra... | 09/29/2011 |
| 20110233736 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ENCAPSULATION AND METHOD OF MANUFACTURE THEREOF A method of manufacture of an integrated circuit packaging system includes: mounting an integrated circuit over a package carrier; mounting a rounded interconnect on the package carrier; mounting a conductive shield over the package carrier, the conductive shield having... | 09/29/2011 |
| 20110227210 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME An embodiment of the invention provides a chip package, which includes: a substrate having an upper surface and a lower surface; a passivation layer located overlying the upper surface of the substrate; a plurality of conducting pad structures disposed overlying the upp... | 09/22/2011 |
| 20110221008 | Semiconductor Packaging and Fabrication Method Using Connecting Plate for Internal Connection A semiconductor package with connecting plate for internal connection comprise: a plurality of chips each having a plurality of contact areas on a top surface; one or more connecting plates having a plurality of electrically isolated connecting plate portions each conne... | 09/15/2011 |
| 20110221053 | PRE-PROCESSING TO REDUCE WAFER LEVEL WARPAGE A method for packaging a stacked integrated circuit (IC) includes pre-processing the stacked IC before releasing the stacked IC from the carrier wafer. Pre-processing reduces wafer warpage and simplifies the packaging process by dicing materials separately. Pre-processi... | 09/15/2011 |
| 20110215459 | INTERCONNECT AND TEST ASSEMBLY INCLUDING AN INTERCONNECT An interconnect includes an elastic body, an electric conductor and a spacer. The elastic body has a first surface, a second surface, a first hole extending from the first surface to the second surface, and a second hole extending from the first surface to the second su... | 09/08/2011 |
| 20110215460 | STACKED SEMICONDUCTOR CHIPS Stacked semiconductor chips. One embodiment provides a device having a first body. A first power semiconductor chip and first external contact elements is provides. A second body includes a second semiconductor chip and second external contact elements. The second body ... | 09/08/2011 |
| 20110210437 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH EXPOSED CONDUCTOR AND METHOD OF MANUFACTURE THEREOF A method of manufacture of an integrated circuit packaging system includes: providing a substrate; forming a component connector on the substrate; forming a resist layer on the substrate with the component connector exposed; forming a vertical insertion cavity in the re... | 09/01/2011 |
| 20110210438 | Thermal Vias In An Integrated Circuit Package With An Embedded Die In a multi-module integrated circuit package having a package substrate and package contacts, a die is embedded in the package substrate with thermal vias that couple hotspots on the embedded die to some of the package contacts.... | 09/01/2011 |
| 20110210439 | Semiconductor Package and Manufacturing Method Thereof A semiconductor package and a manufacturing method thereof are disclosed. The semiconductor package includes a device carrier and a stiffener structure. The device carrier includes at least one insulating layer and at least conductive layer defining at least one trace l... | 09/01/2011 |
| 20110204505 | Semiconductor Device and Method of Forming TMV and TSV in WLCSP Using Same Carrier A semiconductor device has a semiconductor die mounted over a carrier. An encapsulant is deposited over the semiconductor die and carrier. An insulating layer is formed over the semiconductor die and encapsulant. A plurality of first vias is formed through the insulatin... | 08/25/2011 |
| 20110204408 | HIGH THERMAL PERFORMANCE PACKAGING FOR OPTOELECTRONICS DEVICES A novel submount for the efficient dissipation of heat away from a semiconductor light emitting device is described, which also maintains efficient electrical conductivity to the n and p contacts of the device by separating the thermal and electrical conductivity paths.... | 08/25/2011 |
| 20110204506 | Thermal Interface Material Design for Enhanced Thermal Performance and Improved Package Structural Integrity An electronic package 100 comprising a semiconductor device 105, a heat spreader layer 110, and a thermal interface material layer 115 located between the semiconductor device and the heat spreader layer. The thermal interface material layer ... | 08/25/2011 |
| 20110198743 | Method of Manufacturing a Semiconductor Device with a Carrier Having a Cavity and Semiconductor Device A method includes providing a carrier having a first cavity, providing a dielectric foil with a metal layer attached to the dielectric foil, placing a first semiconductor chip in the first cavity of the carrier, and applying the dielectric foil to the carrier.... | 08/18/2011 |
| 20110198744 | LAND GRID ARRAY PACKAGE CAPABLE OF DECREASING A HEIGHT DIFFERENCE BETWEEN A LAND AND A SOLDER RESIST A land grid array (LGA) package including a substrate having a plurality of lands formed on a first surface of the substrate, a semiconductor chip mounted on a second surface of the substrate, a connection portion connecting the semiconductor chip and the substrate, and... | 08/18/2011 |
