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| Application No. | Application Title | Issue Date |
| 20120038002 | IC AND IC MANUFACTURING METHOD Disclosed is a method of manufacturing a vertical bipolar transistor in a CMOS process, comprising implanting an impurity of a first type into a the substrate (100) to form a buried region (150, 260) therein; forming a halo implant (134) using an im... | 02/16/2012 |
| 20120007191 | BIPOLAR DEVICE COMPATIBLE WITH CMOS PROCESS TECHNOLOGY The present invention discloses a bipolar device. An emitter is formed in a semiconductor substrate. A collector is laterally spaced from the emitter in the substrate. A gate terminal is formed on the substrate, defining a space between the emitter and the collector. An... | 01/12/2012 |
| 20110266630 | Semiconductor Device and Method for Manufacturing the Same A configuration of a lateral transistor suited for the hybrid-integration (BiCMOS) of a high-performance lateral transistor (HCBT) and a CMOS transistor, and a method for manufacturing the lateral transistor are provided. A semiconductor device includes a HCBT 100 | 11/03/2011 |
| 20110193174 | Multiple Silicide Integration Structure and Method A structure and method for providing a multiple silicide integration is provided. An embodiment comprises forming a first transistor and a second transistor on a substrate. The first transistor is masked and a first silicide region is formed on the second transistor. Th... | 08/11/2011 |
| 20110133289 | MULTIPLE DOPING LEVEL BIPOLAR JUNCTIONS TRANSISTORS AND METHOD FOR FORMING A process for forming bipolar junction transistors having a plurality of different collector doping densities on a semiconductor substrate and an integrated circuit comprising bipolar junction transistors having a plurality of different collector doping densities. A fir... | 06/09/2011 |
| 20110121402 | SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREOF In a BiCMOS device, a device isolation film separating the bipolar transistor region from the MOS region is taller than the substrate at least where it contacts the bipolar transistor region, and is preferably taller than the same layer where it contacts the MOS transis... | 05/26/2011 |
| 20100289058 | LATERAL BIPOLAR JUNCTION TRANSISTOR A lateral bipolar junction transistor includes an emitter region; a base region surrounding the emitter region; a gate disposed at least over a portion of the base region; a collector region surrounding the base region with an offset between an edge of the gate and the ... | 11/18/2010 |
| 20100252883 | Lateral High-Voltage Semiconductor Devices with Majorities of Both Types for Conduction This invention provides a lateral high-voltage semiconductor device, which is a three-terminal one with two types of carriers for conduction and consists of a highest voltage region and a lowest voltage region referring to the substrate and a surface voltage-sustaining ... | 10/07/2010 |
| 20100244143 | Configuration and fabrication of semiconductor structure having bipolar junction transistor in which non-monocrystalline semiconductor spacing portion controls base-link length A semiconductor structure contains a bipolar transistor (101) and a spacing structure (265-1 or 265-2). The transistor has an emitter (241), a base (243), and a collector (245). The base is formed with an intrinsic... | 09/30/2010 |
| 20100187637 | BIPOLAR DEVICE COMPATIBLE WITH CMOS PROCESS TECHNOLOGY The present invention discloses a bipolar device. An emitter is formed in a semiconductor substrate. A collector is laterally spaced from the emitter in the substrate. A gate terminal is formed on the substrate, defining a space between the emitter and the collector. An... | 07/29/2010 |
| 20100164012 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME A semiconductor device includes a semiconductor substrate including a CMOS region and a bipolar region, a first N well and a first P well in the CMOS region, a PMOS device in the first N well and an NMOS device in the first P well, a deep P well in the bipolar region, a... | 07/01/2010 |
| 20100148276 | BIPOLAR INTEGRATION WITHOUT ADDITIONAL MASKING STEPS The invention relates to a BiMOS semiconductor component having a semiconductor substrate wherein, in a first active region, a depletion-type MOS transistor is formed comprising additional source and drain doping regions of the first conductivity type extending in the d... | 06/17/2010 |
| 20100127318 | BICMOS INTEGRATION OF MULTIPLE-TIMES-PROGRAMMABLE NON-VOLATILE MEMORIES A BiCMOS substrate includes a bipolar area having a buried carrier layer, and a deep trench isolation (DTI) trench extending into the buried carrier layer to form a surface well implant above a buried well implant within the DTI trench, the buried well implant being the... | 05/27/2010 |
| 20100059829 | PROCESS FOR MANUFACTURING A MEMORY DEVICE INCLUDING A VERTICAL BIPOLAR JUNCTION TRANSISTOR AND A CMOS TRANSISTOR WITH SPACERS A bipolar selection transistor and a circuitry MOS transistor for a memory device are formed in a semiconductor body. The bipolar selection transistor is formed by implanting a buried collector, implanting a base region on the buried collector, forming a silicide protec... | 03/11/2010 |
| 20100051946 | POLY-EMITTER TYPE BIPOLAR JUNCTION TRANSISTOR, BIPOLAR CMOS DMOS DEVICE, AND MANUFACTURING METHODS OF POLY-EMITTER TYPE BIPOLAR JUNCTION TRANSISTOR AND BIPOLAR CMOS DMOS DEVICE A poly-emitter type bipolar transistor includes a buried layer formed over an upper portion of a semiconductor substrate, an epitaxial layer formed on the semiconductor substrate, a collector area formed on the epitaxial layer and connected to the buried layer, a base a... | 03/04/2010 |
| 20100032766 | Bipolar Junction Transistor with a Reduced Collector-Substrate Capacitance A process for forming a bipolar junction transistor (BJT) in a semiconductor substrate and a BJT formed according to the process. A buried isolation region is formed underlying BJT structures to isolate the BJT structures from the p-type semi-conductor substrate. To red... | 02/11/2010 |
| 20100019326 | COMPLEMENTARY BIPOLAR SEMICONDUCTOR DEVICE A complementary bipolar semiconductor device (CBi semiconductor device) comprising a substrate of a first conductivity type, active bipolar transistor regions in the substrate, in which the base, emitter and collector of vertical bipolar transistors are arranged, vertic... | 01/28/2010 |
| 20090309167 | Electronic Device and Manufacturing Method Thereof Embodiments relate to a bipolar transistor that includes a body region having a fin structure. At least one terminal region may be formed over at least a portion of the body region. The at least one terminal region may be formed as an epitaxially grown region. Embodimen... | 12/17/2009 |
| 20090278205 | High Voltage BICMOS Device and Method for Manufacturing the Same A high voltage BICMOS device and a method for manufacturing the same, which may improve the reliability of the device by securing a distance between adjacent DUF regions, are provided. The high voltage BICMOS device includes: a reverse diffusion under field (DUF) region... | 11/12/2009 |
| 20090159982 | Bi-CMOS Semiconductor Device and Method of Manufacturing the Same A Bi-CMOS semiconductor device and method for manufacturing the same are provided. An n-well can be formed in a semiconductor substrate, and an NMOS transistor can be provided on the substrate separated from the n-well by a device isolation layer. An NPN bipolar transis... | 06/25/2009 |
| 20090152643 | Semiconductor structures A semiconductor structure is provided. The semiconductor structure comprises a substrate, a first metal-oxide-semiconductor (MOS), a second MOS, a first semiconductor region, and a second semiconductor region. The first and the second MOSs are formed on the substrate. T... | 06/18/2009 |
| 20090127630 | Method for Fabricating Isolated Integrated Semiconductor Structures An integrated semiconductor structure and a method for fabricating an integrated semiconductor structure in a bulk semiconductor wafer.... | 05/21/2009 |
| 20090127631 | SEMICONDUCTOR DEVICE HAVING ELEMENT ISOLATION REGION AND METHOD FOR MANUFACTURE THEREOF An n-type buried diffusion layer is formed on the surface layer of the prescribed area of a p-type silicon substrate, and a p-type first high-concentration isolation diffusion layer is formed in the silicon substrate so as to surround the buried diffusion layer. An n-ty... | 05/21/2009 |
| 20090127629 | Method of forming npn and pnp bipolar transistors in a CMOS process flow that allows the collectors of the bipolar transistors to be biased differently than the substrate material NPN and PNP bipolar junction transistors are formed in a semiconductor substrate material in a double polysilicon CMOS process flow in a manner that allows the collectors of both of the npn and pnp bipolar transistors to be biased differently than the bias that is place... | 05/21/2009 |
| 20090096033 | ISOLATION TRENCH WITH ROUNDED CORNERS FOR BiCMOS PROCESS A semiconductor device comprising a first transistor device on or in a semiconductor substrate and a second transistor device on or in the substrate. The device further comprises an insulating trench located between the first transistor device and the second transistor ... | 04/16/2009 |
| 20090079007 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF The present invention can prevent occurrence of an off-leak current in the NMISFETs formed over the Si (110) substrate and having a silicided source/drain region. The semiconductor device includes N channel MISFETs (Metal Insulator Semiconductor Field Effect Transistors... | 03/26/2009 |
| 20090057774 | Methods of forming bipolar transistors by silicide through contact and structures formed thereby Methods and associated structures of forming a microelectronic device are described. Those methods may comprise forming an opening in a masking layer, implanting an amorphizing species into a silicon region disposed within the opening, wherein the silicon region compris... | 03/05/2009 |
| 20090057773 | Semiconductor device and method of manufacturing the same A method of manufacturing a semiconductor device including a complementary metal oxide semiconductor (CMOS) and a bipolar junction transistor (BJT), the method comprising the steps of: forming a gate oxide layer on a substrate having a p-type and an n-type well; removin... | 03/05/2009 |
| 20090045467 | BIPOLAR TRANSISTOR FINFET TECHNOLOGY This document discusses, among other things, apparatus having at least one CMOS transistor overlying a substrate; and at least one finned bipolar transistor overlying the substrate and methods for making the apparatus.... | 02/19/2009 |
| 20080265333 | STRUCTURE AND METHOD FOR ENHANCED TRIPLE WELL LATCHUP ROBUSTNESS Disclosed is a triple well CMOS device structure that addresses the issue of latchup by adding an n+ buried layer not only beneath the p-well to isolate the p-well from the p-substrate but also beneath the n-well. The structure eliminates the spacing issues between the ... | 10/30/2008 |
| 20080258231 | SEMICONDUCTOR DEVICE A semiconductor device includes an inverter having an NMOSFET and a PMOSFET having sources, drains and gate electrodes respectively, the drains being connected to each other and the gate electrodes being connected to each other, and a pnp bipolar transistor including a ... | 10/23/2008 |
| 20080237731 | Semiconductor device and method of producing the same A semiconductor device includes a semiconductor layer formed on an insulation layer and having an MOS (Metal Oxide Semiconductor) transistor area and a bi-polar transistor area; an MOS transistor formed in the MOS transistor area; and a bi-polar transistor formed in the... | 10/02/2008 |
| 20080224227 | BiCMOS performance enhancement by mechanical uniaxial strain and methods of manufacture A BiCMOS device with enhanced performance by mechanical uniaxial strain is provided. A first embodiment of the present invention includes an NMOS transistor, a PMOS transistor, and a bipolar transistor formed on different areas of the substrate. A first contact etch sto... | 09/18/2008 |
| 20080203490 | BIPOLAR TRANSISTOR WITH RAISED EXTRINSIC SELF-ALIGNED BASE USING SELECTIVE EPITAXIAL GROWTH FOR BICMOS INTEGRATION High performance bipolar transistors with raised extrinsic self-aligned base are integrated into a BiCMOS structure containing CMOS devices. By forming pad layers and raising the height of an intrinsic base layer relative to the source and drain of preexisting CMOS devi... | 08/28/2008 |
| 20080197422 | Planar combined structure of a bipolar junction transistor and N-type/P-type metal semiconductor field-effect transistors and method for forming the same A planar combined structure of a bipolar junction transistor (BJT) and n-type/p-type metal semiconductor field-effect transistors (MESFETs) and a method for forming the structure. The n-type GaN MESFET is formed at the same time when an inversion region (an emitter regi... | 08/21/2008 |
| 20080191238 | Bipolar Mosfet Devices and Methods For Their Use According to the invention there is provided a semiconductor device including: at least one cell including a base region of a first conductivity type having disposed therein at least one emitter region of a second conductivity type; a first well region of a second condu... | 08/14/2008 |
| 20080169513 | Emitter Ballasting by Contact Area Segmentation in ESD Bipolar Based Semiconductor Component Integrated circuits (ICs) utilize bipolar transistors in electro-static discharge (ESD) protection circuits to shunt discharge currents during ESD events to protect the components in the ICs. Bipolar transistors are subject to non-uniform current crowding across the emi... | 07/17/2008 |
| 20080006826 | THIN-FILM SEMICONDUCTOR DEVICE, LATERAL BIPOLAR THIN-FILM TRANSISTOR, HYBRID THIN-FILM TRANSISTOR, MOS THIN-FILM TRANSISTOR, AND METHOD OF FABRICATING THIN-FILM TRANSISTOR In a lateral bipolar transistor including an emitter, a base and a collector which are formed in a semiconductor thin film formed on an insulating substrate, the semiconductor thin film is a semiconductor thin film which is crystallized in a predetermined direction. In ... | 01/10/2008 |
| 20080001234 | Hybrid Field Effect Transistor and Bipolar Junction Transistor Structures and Methods for Fabricating Such Structures Semiconductor device structures that integrate field effect transistors and bipolar junction transistors on a single substrate, such as a semiconductor-on-insulator substrate, and methods for fabricating such hybrid semiconductor device structures. The field effect and ... | 01/03/2008 |
| 20070284672 | CURRENT LIMITING MOSFET STRUCTURE FOR SOLID STATE RELAYS A current-limiting circuit for limiting rising of a current above a predetermined level. The circuit including forward- and reverse-conducting devices, each device including a MOS and a bipolar transistor, wherein ON-resistance of one of the devices is used instead of a... | 12/13/2007 |
