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| Application No. | Application Title | Issue Date |
| 20120126328 | SEMICONDUCTOR DEVICE A semiconductor device includes an epitaxial layer having a first conductive type, and at least one first semiconductor layer and a second semiconductor layer having a second conductive type. The first semiconductor layer is disposed in the epitaxial layer of a peripher... | 05/24/2012 |
| 20120126329 | FINFET PROCESS COMPATIBLE NATIVE TRANSISTOR Provided is a top-channel only finFET device. The devices described herein may provide a native device that is compatible with a finFET process flow. A gate may be formed on the top of a fin providing the channel region of the device. In an embodiment, the gate is provi... | 05/24/2012 |
| 20120104501 | Semiconductor apparatus and method of manufacturing semiconductor apparatus A semiconductor apparatus includes: an MOS type field effect transistor formed on a semiconductor substrate and having a first gate electrode set at a predetermined impurity concentration; and a charge modulation device formed on the semiconductor substrate and having a... | 05/03/2012 |
| 20120104500 | SHALLOW TRENCH ISOLATION RECESS REPAIR USING SPACER FORMATION PROCESS A method of forming a semiconductor device includes forming a spacer layer over a plurality of transistor gate structures, the transistor gate structures being formed over both active and shallow trench isolation (STI) regions of a substrate. The spacer layer is subject... | 05/03/2012 |
| 20120104502 | METHOD OF PRODUCING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE Disclosed is a method of producing a semiconductor device, able to form a source/drain of a Schottky junction (FET) with simple steps and able to improve the device characteristics. A gate is formed on an element region defined in a silicon substrate layer by element is... | 05/03/2012 |
| 20120104503 | TRANSISTOR STRUCTURE WITH SILICIDED SOURCE AND DRAIN EXTENSIONS AND PROCESS FOR FABRICATION A transistor is formed in a semiconductor substrate with a gate over a channel region, source/drain extension regions in the substrate adjacent the channel region, and source/drain regions in the substrate adjacent the source/drain extension regions. Silicide is formed ... | 05/03/2012 |
| 20120104504 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME Provided are a semiconductor device and a fabricating method thereof. The semiconductor device includes a substrate having a trench that defines an active region, an isolation layer that buries the trench, a pro-oxidant region formed at an upper corner portion of the tr... | 05/03/2012 |
| 20120080754 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE The semiconductor device includes a first transistor including a first impurity layer containing boron or phosphorus, a first epitaxial layer formed above the first impurity layer, a first gate electrode formed above the first epitaxial layer with a first gate insulatin... | 04/05/2012 |
| 20120080755 | Methods for Forming Gates in Gate-Last Processes and Gate Areas formed by the Same Methods are provided for forming gates in gate-last processes. The methods may include performing chemical mechanical polishing (CMP) on an interlayer dielectric (ILD) that is on a plurality of dummy gates, each of the plurality of dummy gates including a gate mask in a... | 04/05/2012 |
| 20120068270 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE DEVICE A semiconductor device includes a first transistor including a gate electrode formed on semiconductor substrate with a gate insulating film interposed therebetween, a first sidewall formed on each side surface of the first gate electrode, and a source/drain diffusion la... | 03/22/2012 |
| 20120068268 | TRANSISTOR STRUCTURE AND METHOD OF FABRICATING THE SAME A method of fabricating a transistor structure includes the step of providing a substrate having a gate thereon. Then, a first spacer is formed at two sides of the gate. After that, an LDD region is formed in the substrate at two sides of the gate. Later, a second space... | 03/22/2012 |
| 20120068269 | Producing a perfect P-N junction This patent disclosure presents circuits, system, and method to produce an ideal memory cell and a method to produce a perfect PN junction without undesirable junction voltage and leakage current. These new inventions finally perfect the art to produce PN junction diode... | 03/22/2012 |
| 20120049256 | SEMICONDUCTOR DEVICE HAVING LOW RESISTIVITY REGION UNDER ISOLATION LAYER A semiconductor device includes a buried well, first and second active regions, an isolation layer, and a low resistance region. The buried well is disposed on a substrate and has impurity ions of a first conductivity type. The first and second active regions are dispos... | 03/01/2012 |
| 20120049287 | TRENCH ISOLATION MOS P-N JUNCTION DIODE DEVICE AND METHOD FOR MANUFACTURING THE SAME A trench isolation metal-oxide-semiconductor (MOS) P-N junction diode device and a manufacturing method thereof are provided. The trench isolation MOS P-N junction diode device is a combination of an N-channel MOS structure and a lateral P-N junction diode, wherein a po... | 03/01/2012 |
| 20120049286 | Gate Electrodes of a Semiconductor Device Formed by a Hard Mask and Double Exposure in Combination with a Shrink Spacer When forming complex gate electrode structures, a double exposure double etch strategy may be applied, in which the lateral distance in the width direction of the gate electrode structures may be defined prior to forming mask features for defining the gate length. In th... | 03/01/2012 |
| 20120049290 | SEMICONDUCTOR DEVICE In order to reduce parasitic inductance of a main circuit in a power supply circuit, a non-insulated DC-DC converter is provided having a circuit in which a power MOS•FET for a high-side switch and a power MOS•FET for a low-side switch are connected in series. In th... | 03/01/2012 |
| 20120049285 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME A method of fabricating a semiconductor device and a semiconductor device are provided. The method includes method of fabricating a semiconductor device including providing a semiconductor substrate having a first semiconductor device region and a second semiconductor d... | 03/01/2012 |
| 20120051164 | MEMORY CELL, METHODS OF MANUFACTURING MEMORY CELL, AND MEMORY DEVICE HAVING THE SAME A memory cell includes a selection transistor on a substrate and an antifuse on the substrate. The selection transistor includes a first gate connected to a read word line, a first gate insulation layer that insulates the first gate from the substrate, a first source re... | 03/01/2012 |
| 20120043613 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME A disclosed semiconductor device includes multiple gate electrodes disposed on a semiconductor substrate; and multiple sidewall spacers disposed on sidewalls of the gate electrodes. The thickness of the sidewall spacers is larger on the sidewalls along longer sides of t... | 02/23/2012 |
| 20120043612 | Device Layout in Integrated Circuits to Reduce Stress from Embedded Silicon-Germanium An integrated circuit including one or more transistors in which source and drain regions are formed as embedded silicon-germanium (eSiGe). Guard ring structures in the integrated circuit are formed in single-crystal silicon, rather than in eSiGe. In one example, p-chan... | 02/23/2012 |
| 20120044741 | Semiconductor device having memory unit, method of writing to or reading from memory unit, and semiconductor device manufacturing method A first semiconductor device is formed over a substrate and includes a first insulation film, a first electrode, and a first diffusion layer. A second semiconductor device is formed over a substrate and includes a second insulation film, a second electrode, and a second... | 02/23/2012 |
| 20120037995 | SEMICONDUCTOR DEVICE AND RELATED METHOD OF FABRICATION A semiconductor device comprises a device isolation pattern, an active region, a gate pattern, a first source/drain region, and a first barrier region. The device isolation pattern defines an active portion in a semiconductor substrate and the active portion comprises f... | 02/16/2012 |
| 20120037917 | LOW INTERCONNECT RESISTANCE INTEGRATED SWITCHES Circuits and systems comprising one or more switches are provided. A circuit includes a first switch formed on a substrate; and a second switch formed on the substrate, the second switch including a first terminal coupled to a third terminal of the first switch. A syste... | 02/16/2012 |
| 20120037996 | SRAM BIT CELL WITH SELF-ALIGNED BIDIRECTIONAL LOCAL INTERCONNECTS Improved SRAMs are formed with significantly reduced local interconnect to gate shorts, by a technique providing bidirectional, self-aligned local interconnects, employing a gate hard mask over portions of the gates not connected to the local interconnects. Embodiments ... | 02/16/2012 |
| 20120037997 | METHOD AND APPARATUS FOR WORD LINE DRIVER WITH DECREASED GATE RESISTANCE A semiconductor device comprises first, second, and third. The first conductor is a gate conductor formed above an oxide region over a substrate and having a contact. The second conductor is coupled to the contact and extends across a width of the oxide region. The seco... | 02/16/2012 |
| 20120032267 | DEVICE AND METHOD FOR UNIFORM STI RECESS A semiconductor device and method for forming the semiconductor device include forming structures in a semiconductor substrate. The structures have two or more different spacings between them. A dielectric material is deposited in the spacings. Ion species are implanted... | 02/09/2012 |
| 20120032268 | Layout and Process of Forming Contact Plugs A device includes a semiconductor substrate including an active region, a gate electrode directly over the active region, and a gate contact plug over and electrically coupled to the gate electrode. The gate contact plug includes at least a portion directly over, and ve... | 02/09/2012 |
| 20120032269 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD FOR FABRICATING THE SAME Provided are a semiconductor integrated device and a method for fabricating the same. The semiconductor integrated circuit includes a semiconductor substrate including a first dopant, a first conductive layer pattern formed on the semiconductor substrate, an interlayer ... | 02/09/2012 |
| 20120032270 | DEPLETION MODE FIELD EFFECT TRANSISTOR FOR ESD PROTECTION A field effect transistor is provided having a reduced drain capacitance per unit gate width. A gate electrode 21 (G) having a plurality of sides is formed in first-conductivity first semiconductor region 14. Drain region 18D (D) is formed inside th... | 02/09/2012 |
| 20120025282 | Raised Source/Drain Field Effect Transistor In one exemplary embodiment of the invention, a semiconductor structure includes: a substrate; and a plurality of devices at least partially overlying the substrate, where the plurality of devices include a first device coupled to a second device via a first raised sour... | 02/02/2012 |
| 20120025317 | SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FABRICATING THE SAME A semiconductor device structure and a method for fabricating the same. A method for fabricating semiconductor device structure includes forming gate lines on a semiconductor substrate; forming gate sidewall spacers surrounding the gate lines; forming respective source/... | 02/02/2012 |
| 20120025316 | Process for Forming FINS for a FinFET Device An integrated fin-based field effect transistor (FinFET) and method of fabricating such devices on a bulk wafer with EPI-defined fin heights over shallow trench isolation (STI) regions. The FinFET channels overlie the STI regions within the semiconductor bulk, while the... | 02/02/2012 |
| 20120025325 | Asymmetric Segmented Channel Transistors Structures, layouts and methods of forming integrated circuits are described. In various embodiments, the current invention includes an asymmetric segmented transistor. The asymmetric segmented transistor includes a source region and a drain region disposed within an ac... | 02/02/2012 |
| 20120025318 | Reduced Topography in Isolation Regions of a Semiconductor Device by Applying a Deposition/Etch Sequence Prior to Forming the Interlayer Dielectric Contact failures in sophisticated semiconductor devices may be reduced by relaxing the pronounced surface topography in isolation regions prior to depositing the interlayer dielectric material system. To this end, a deposition/etch sequence may be applied in which a fil... | 02/02/2012 |
| 20120018619 | Method of Resetting a Photosite, and Corresponding Photosite A method of resetting a photosite is disclosed. Photogenerated charges accumulated in the photosite are reset by recombining the photogenerated charges with charges of opposite polarity.... | 01/26/2012 |
| 20120012936 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD A semiconductor device including a semiconductor substrate having a logic formation region where a logic device is formed; a first impurity region formed in an upper surface of the semiconductor substrate in the logic formation region; a second impurity region formed in... | 01/19/2012 |
| 20120007187 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING GATE AND METAL LINE THEREOF A gate in a semiconductor device is formed to have a dummy gate pattern that protects a gate. Metal lines are formed to supply power for a semiconductor device and transfer a signal. A semiconductor device includes a quad coupled receiver type input/output buffer. The s... | 01/12/2012 |
| 20120007186 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME A semiconductor device includes a first gate electrode buried within a semiconductor substrate, a second gate electrode buried within a silicon growth layer disposed on the semiconductor substrate, and a bit line disposed on an interlayer insulating layer disposed on th... | 01/12/2012 |
| 20120007189 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND A METHOD OF MANUFACTURING THE SAME To provide a circuit layout design method that can prevent degradation of the circuit reliability even in highly miniaturized circuit cells. In order to prevent noise from a power supply potential or a reference potential with a large poten... | 01/12/2012 |
| 20120007185 | Novel method to tune narrow width effect with raised S/D structure A method (and semiconductor device) of fabricating a semiconductor device adjusts gate threshold (Vt) of a field effect transistor (FET) with raised source/drain (S/D) regions. A halo region is formed in a two-step process that includes implanting dopants using conventi... | 01/12/2012 |
