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| Application No. | Application Title | Issue Date |
| 20120007179 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF A high voltage/power semiconductor device using a low voltage logic well is provided. The semiconductor device includes a substrate, a first well region formed by being doped in a first location on a surface of the substrate, a second well region formed by being doped w... | 01/12/2012 |
| 20110316079 | Shallow Junction Formation and High Dopant Activation Rate of MOS Devices A semiconductor structure comprises a gate stack in a semiconductor substrate and a lightly doped source/drain (LDD) region in the semiconductor substrate. The LDD region is adjacent to a region underlying the gate stack. The LDD region comprises carbon and an n-type im... | 12/29/2011 |
| 20110298049 | CMOS Device with Raised Source and Drain Regions A semiconductor structure includes a semiconductor substrate comprising a PMOS region and an NMOS region; a PMOS device in the PMOS region; and an NMOS device in the NMOS region. The PMOS device includes a first gate stack on the semiconductor substrate; a first offset ... | 12/08/2011 |
| 20110254068 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF The present invention provides a semiconductor device in which a bottom-gate TFT or an inverted stagger TFT arranged in each circuit is suitably constructed in conformity with the functionality of the respective circuits, thereby attaining an improvement in the operatin... | 10/20/2011 |
| 20110254089 | SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF FABRICATING SAME A semiconductor integrated circuit comprising thin-film transistors in each of which the second wiring is prevented from breaking at steps. A silicon nitride film is formed on gate electrodes and on gate wiring extending from the gate electrodes. Substantially triangula... | 10/20/2011 |
| 20110221000 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE A method for manufacturing a semiconductor device includes forming a first gate electrode on a semiconductor substrate in a first transistor region; forming a channel dose region; and forming a first source extension region, wherein the channel dose region is formed by ... | 09/15/2011 |
| 20110186928 | Semiconductor device A semiconductor device according to the present invention includes a semiconductor substrate of a first conductivity type having a top surface and a rear surface, a semiconductor layer of a second conductivity type formed on the top surface of the semiconductor substrat... | 08/04/2011 |
| 20110133273 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF A semiconductor device including a low-concentration impurity region formed on the drain side of an n-type MIS transistor, in a non-self-aligned manner with respect to an end portion of the gate electrode. A high-concentration impurity region is placed with a specific o... | 06/09/2011 |
| 20110108917 | SEMICONDUCTOR DEVICE WITH HIGH VOLTAGE TRANSISTOR A semiconductor device includes: a p-type active region; a gate electrode traversing the active region; an n-type LDD region having a first impurity concentration and formed from a drain side region to a region under the gate electrode; a p-type channel region having a ... | 05/12/2011 |
| 20110079850 | SEMICONDUCTOR STRUCTURE INCLUDING HIGH VOLTAGE DEVICE A high voltage device includes a substrate with a device region defined thereon. A gate stack is disposed on the substrate in the device region. A channel region is located in the substrate beneath the gate stack, while a first diffusion region is located in the substra... | 04/07/2011 |
| 20110073946 | LDMOS TRANSISTOR An LDMOS transistor (100) on a substrate (70a, 70b) of a first conductivity type, comprises a source region (10) with a source portion (73) and a drain region (12). The source portion and drain region are of a seco... | 03/31/2011 |
| 20110012197 | METHOD OF FABRICATING TRANSISTORS AND A TRANSISTOR STRUCTURE FOR IMPROVING SHORT CHANNEL EFFECT AND DRAIN INDUCED BARRIER LOWERING A method of fabricating transistors includes: providing a substrate including an N-type well and P-type well; forming a first gate on the N-type well and a second gate on the P-type well, respectively; forming a third spacer on the first gate; forming an epitaxial layer... | 01/20/2011 |
| 20100181618 | EXTENDED DRAIN TRANSISTOR AND METHOD OF MANUFACTURING THE SAME An extended drain transistor (100) comprising a substrate (101), a gate (103) formed on the substrate (100), the gate (103) having a first side wall (104) and a second side wall (105) opposing the first side wall (104<... | 07/22/2010 |
| 20100096698 | STRESS ENHANCED TRANSISTOR Stress enhanced MOS transistors are provided. A semiconductor device is provided that comprises a semiconductor-on-insulator structure, a gate insulator layer, a source region, a drain region and a conductive gate overlying the gate insulator layer. The semiconductor-on... | 04/22/2010 |
| 20100078721 | SEMICONDUCTOR DEVICE A field-effect transistor (142) includes a lowly p-doped region 110 formed on a surface of a substrate (102), an n-doped drain region 112 and n-doped source region 114 arranged on a surface of the lowly p-doped region 110, and a... | 04/01/2010 |
| 20100065910 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME A semiconductor device includes a first MISFET and a second MISFET, wherein the first MISFET includes a semiconductor substrate 100, a first gate insulating film 101a and a first gate electrode 102a formed on the first region of the se... | 03/18/2010 |
| 20100038713 | Self-aligned tunneling pocket in field-effect transistors and processes to form same A microelectronic device includes a tunneling pocket within an asymmetrical semiconductive body including source- and drain wells. The tunneling pocket is formed by a self-aligned process by removing a dummy gate electrode from a gate spacer and by implanting the tunnel... | 02/18/2010 |
| 20100032753 | MOS Transistor Including Extended NLDD Source-Drain Regions For Improved Ruggedness A MOS transistor includes a conductive gate insulated from a semiconductor layer by a dielectric layer, first and second lightly-doped diffusion regions formed self-aligned to respective first and second edges of the conductive gate, a first diffusion region formed self... | 02/11/2010 |
| 20090321797 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE A method of manufacturing a semiconductor device including at least one step of: forming a transistor on and/or over a semiconductor substrate; forming silicide on and/or over a gate electrode and a source/drain region of the transistor; removing an uppermost oxide film... | 12/31/2009 |
| 20090315110 | High voltage MOS array with gate contact on extended drain region In an extended drain MOS device used in high voltage applications, switching characteristics are improved by providing for at least one base contact in the active region in the extended drain space.... | 12/24/2009 |
| 20090294850 | METHOD TO TAILOR LOCATION OF PEAK ELECTRIC FIELD DIRECTLY UNDERNEATH AN EXTENSION SPACER FOR ENHANCED PROGRAMMABILITY OF A PROMPT-SHIFT DEVICE The invention provides a method to enhance the programmability of a prompt-shift device, which reduces the programming time to sub-millisecond times, by altering the extension and halo implants, instead of simply omitting the same from one side of the device as is the c... | 12/03/2009 |
| 20090294823 | METHOD OF MANUFACTURING A SEMICONDUCTOR INTEGRATED CIRCUIT USING A SELECTIVE DISPOSAL SPACER TECHNIQUE AND SEMICONDUCTOR INTEGRATED CIRCUIT MANUFACTURED THEREBY Methods of manufacturing a semiconductor integrated circuit using selective disposable spacer technology and semiconductor integrated circuits manufactured thereby. The method includes providing a semiconductor substrate; forming gate patterns on the semiconductor subst... | 12/03/2009 |
| 20090289300 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME First and second gate insulating films are formed so as to cover at least the upper corner of first and second fin-shaped semiconductor regions. The radius of curvature r1′ of the upper corner of the first fin-shaped semiconductor region located outside the fir... | 11/26/2009 |
| 20090278170 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF A method for manufacturing a semiconductor device includes providing a substrate having at least a gate structure formed thereon, forming LDDs in the substrate respectively at two side of the gate structure and a spacer at sidewalls of the gate structure, forming a sour... | 11/12/2009 |
| 20090242983 | SEMICONDUCTOR DEVICE HAVING A FIELD EFFECT TRANSISTOR USING A HIGH DIELECTRIC CONSTANT GATE INSULATING FILM AND MANUFACTURING METHOD OF THE SAME In a method for manufacturing a semiconductor device having an N-channel field effect transistor, the N-channel field effect transistor is formed by a process including the steps of forming a high dielectric constant gate insulating film on a substrate, forming a gate e... | 10/01/2009 |
| 20090224319 | Highly Conductive Shallow Junction Formation The invention relates to a method of forming a shallow junction. The method (100) comprises forming source/drain extension regions with a non-amorphizing tail implant (105) which is annealed conventionally (spike/RTP) and amorphizing implant which is re-gr... | 09/10/2009 |
| 20090166737 | Method for Manufacturing a Transistor A method for manufacturing a transistor is disclosed, which is capable of improving matching characteristics of regions within a transistor or among transistors on a wafer, from wafer-to-wafer, or from lot-to-lot. The method includes forming a photoresist pattern on a s... | 07/02/2009 |
| 20090152629 | METHODS OF SELECTIVELY OXIDIZING SEMICONDUCTOR STRUCTURES, AND STRUCTURES RESULTING THEREFROM Methods for selectively oxidizing a semiconductor structure include generating a gas cluster ion beam comprising an oxidizing source gas, directing the gas cluster ion beam to a region of a substrate adjacent a conductive line and exposing the region to the gas cluster ... | 06/18/2009 |
| 20090140335 | Drain-Extended Field Effect Transistor A drain-extended field effect transistor includes a drain contact region and a drain extension region. The drain-extended field effect transistor further includes an electrostatic discharge protection region that is electrically connected between the drain contact regio... | 06/04/2009 |
| 20090121286 | Integrated Circuit Comprising a Field Effect Transistor and Method of Fabricating the Same An integrated circuit includes a field effect transistor including: a gate electrode disposed adjacent to a surface of semiconductor substrate and a source/drain region disposed in the semiconductor substrate and adjacent to the surface. A net dopant concentration of a ... | 05/14/2009 |
| 20090096023 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE A method for manufacturing a semiconductor device that eliminates the cause of increase in leakage current and therefore suppresses power increase in a highly integrated circuit by forming a shallow junction using a dopant-containing oxide film after etching a semicondu... | 04/16/2009 |
| 20090090980 | ASYMMETRIC-LDD MOS DEVICE The present invention proposes a new asymmetric-lightly-doped drain (LDD) metal oxide semiconductor (MOS) transistor that is fully embedded in a CMOS logic. The radio frequency (RF) power performance of both conventional and asymmetric MOS transistor is measured and com... | 04/09/2009 |
| 20090072310 | SEMICONDUCTOR STRUCTURE INCLUDING HIGH VOLTAGE DEVICE A high voltage device includes a substrate with a device region defined thereon. A gate stack is disposed on the substrate in the device region. A channel region is located in the substrate beneath the gate stack, while a first diffusion region is located in the substra... | 03/19/2009 |
| 20090065865 | Semiconductor Device and Method of Fabricating the Same Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device can include a transistor structure including a gate electrode and a first channel region and source/drain regions on a substrate, and a second channel region and source/d... | 03/12/2009 |
| 20090057760 | SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF A semiconductor device and fabricating method thereof are disclosed, by which channel mobility is enhanced and by which effect of flicker noise can be minimized. Embodiments relate to a method of fabricating a semiconductor device which includes forming a first epi-laye... | 03/05/2009 |
| 20090057761 | Fin field effect transistor and method of manufacturing the same Provided are a FinFET and a method of manufacturing the same. A FinFET may include at least one active fin, at least one gate insulating layer pattern, a first electrode pattern, a second electrode pattern and at least one pair of source/drain expansion regions. The at ... | 03/05/2009 |
| 20090050962 | MOSFET WITH ISOLATION STRUCTURE FOR MONOLITHIC INTEGRATION AND FABRICATION METHOD THEREOF A MOSFET device with an isolation structure for a monolithic integration is provided. A P-type MOSFET includes a first N-well disposed in a P-type substrate, a first P-type region disposed in the first N-well, a P+ drain region disposed in the first P-type region, a fir... | 02/26/2009 |
| 20090050963 | STRESSED MOS DEVICE AND METHODS FOR ITS FABRICATION Stressed MOS devices and methods for their fabrication are provided. The stressed MOS device comprises a T-shaped gate electrode formed of a material having a first Young's modulus. The T-shaped gate electrode includes a first vertical portion and a second horizontal po... | 02/26/2009 |
| 20090039426 | EXTREMELY-THIN SILICON-ON-INSULATOR TRANSISTOR WITH RAISED SOURCE/DRAIN An extremely-thin silicon-on-insulator transistor is provided that includes a buried oxide layer above a substrate, a silicon layer above the buried oxide layer, a gate stack on the silicon layer, a nitride liner on the silicon layer and adjacent to the gate stack, an o... | 02/12/2009 |
| 20090039427 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME A semiconductor device includes an n channel conductivity type FET having a channel formation region formed in a first region on a main surface of a semiconductor substrate and a p channel conductivity type FET having a channel formation region formed in a second region... | 02/12/2009 |
