Bizarre Patents
Behavior Modification Wristwatch
A wristwatch including a watch band and a watch body having an octagon shaped perimeter and being red in color and having the word STOP thereon to resemble a stop sign.
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| Application No. | Application Title | Issue Date |
| 20120001245 | Recessed Access Device for a Memory Semiconductor memory devices having recessed access devices are disclosed. In some embodiments, a method of forming the recessed access device includes forming a device recess in a substrate material that extends to a first depth in the substrate that includes a gate ox... | 01/05/2012 |
| 20110095349 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME A technique for enhancing the performance of a memory- and logic-equipped semiconductor device is provided. The semiconductor device comprises a semiconductor substrate (1), an insulating layer (19) on the semiconductor substrate (1), a plurality of... | 04/28/2011 |
| 20110057240 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME A semiconductor device includes a plurality of conduction plugs disposed on an active region, a bit line connected to a conduction plug of the plurality of conduction plugs which is disposed in a central portion of the active region, and storage nodes connected with con... | 03/10/2011 |
| 20110049600 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME In a method of manufacturing a semiconductor device, first contact holes reaching diffusion regions of a cell transistor, bit line contact holes reaching diffusion regions of the cell transistor, and interconnect grooves communicating with the bit line contact holes are... | 03/03/2011 |
| 20100283093 | Structure and Method to Form EDRAM on SOI Substrate A memory device is provided that in one embodiment includes a trench capacitor located in a semiconductor substrate including an outer electrode provided by the semiconductor substrate, an inner electrode provided by a conductive fill material, and a node dielectric lay... | 11/11/2010 |
| 20100187587 | MEMORY CELL STRUCTURE AND METHOD FOR FABRICATION THEREOF A memory cell includes a substrate, an access transistor and a storage capacitor. The access transistor comprising a gate stack disposed on the substrate, and a first and second diffusion region located on a first and second opposing sides of the gate stack. The storage... | 07/29/2010 |
| 20100072532 | Recessed Access Device For A Memory Semiconductor memory devices having recessed access devices are disclosed. In some embodiments, a method of forming the recessed access device includes forming a device recess in a substrate material that extends to a first depth in the substrate that includes a gate ox... | 03/25/2010 |
| 20100038694 | SPLIT-GATE DRAM WITH MUGFET, DESIGN STRUCTURE, AND METHOD OF MANUFACTURE A semiconductor structure for a dynamic random access memory cell, the structure including: a fin of a fin-type field effect transistor (FinFET) device formed over and spaced apart from a conductive region of a substrate; a storage capacitor connected to a first end of ... | 02/18/2010 |
| 20100019301 | Dynamic random access memory structure A dynamic random access memory structure includes a recessed-gate transistor disposed in the substrate; a trench capacitor structure disposed in the substrate and electrically connected to a first source/drain of the recessed-gate transistor; a first conductive structur... | 01/28/2010 |
| 20090315092 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF A semiconductor device provided with a field-effect transistor, the field-effect transistor including: a active region defined by element isolating region 3 formed on semiconductor substrate 1; gate electrode 5 provided so as to intersect the active... | 12/24/2009 |
| 20090184357 | SOI BASED INTEGRATED CIRCUIT AND METHOD FOR MANUFACTURING A SOI based integrated circuit and method for manufacturing a SOI based integrated circuit is disclosed. One embodiment provides an integrated circuit having a silicon-on-insulator carrier including a substrate, a buried insulating layer on the substrate and a semicondu... | 07/23/2009 |
| 20090166703 | MEMORY DEVICE WITH A LENGTH-CONTROLLABLE CHANNEL A memory device is provided. The memory device includes a substrate, a trench having an upper portion and a lower portion formed in the substrate, a trench capacitor formed in the lower portion of the trench, a collar dielectric layer formed on a sidewall of the trench ... | 07/02/2009 |
| 20090166702 | TRENCH-TYPE SEMICONDUCTOR DEVICE STRUCTURE A trench-type semiconductor device structure is disclosed. The structure includes a semiconductor substrate, a gate dielectric layer and a substrate channel structure. The semiconductor substrate includes a trench having an upper portion and a lower portion. The upper p... | 07/02/2009 |
| 20090101958 | TRENCH SOI-DRAM CELL AND METHOD FOR MAKING THE SAME The present invention relates to a trench silicon-on-insulator (SOI) dynamic random access memory (DRAM) cell and a method for making the same. A source and a drain are utilized to each connect to one of two semiconductor conductive units on an external side of a main b... | 04/23/2009 |
| 20090096001 | Integrated Circuit and Method of Manufacturing the Same A method of manufacturing an integrated circuit includes: forming a trench in a substrate, forming a high-k dielectric layer lining the trench, and removing a section of the high-k dielectric layer from the trench via an isotropic dry etch process.... | 04/16/2009 |
| 20090072290 | SOI CMOS COMPATIBLE MULTIPLANAR CAPACITOR An isolated shallow trench isolation portion is formed in a top semiconductor portion of a semiconductor-on-insulator substrate along with a shallow trench isolation structure. A trench in the shape of a ring is formed around a doped top semiconductor portion and filled... | 03/19/2009 |
| 20090039403 | SEMICONDUCTOR DEVICE INCLUDING AN IMPROVED CAPACITOR AND METHOD FOR MANUFACTURING THE SAME In a semiconductor device according to embodiments of the invention, a capacitor includes a storage electrode having a cylindrical storage conductive layer pattern and connecting members formed on the upper portion of the cylindrical storage conductive layer pattern. Th... | 02/12/2009 |
| 20090020798 | TRANSISTOR STRUCTURE AND METHOD OF MAKING THE SAME A transistor structure includes a gate trench. The gate trench includes a bottle-shape bottom. The bottle-shape bottom includes a first conductive material wider than its top. The top includes a second material in a substrate, a gate structure on the gate trench and ele... | 01/22/2009 |
| 20090008693 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME A technique for enhancing the performance of a memory- and logic-equipped semiconductor device is provided. The semiconductor device comprises a semiconductor substrate (1), an insulating layer (19) on the semiconductor substrate (1), a plurality of... | 01/08/2009 |
| 20080258197 | SEMICONDUCTOR-INSULATOR-SILICIDE CAPACITOR A semiconductor-insulator-silicide (SIS) capacitor is formed by depositing a thin silicon containing layer on a salicide mask dielectric layer, followed by lithographic patterning of the stack and metallization of the thin silicon containing layer and other exposed semi... | 10/23/2008 |
| 20080246069 | Folded Node Trench Capacitor A trench capacitor is filled with a set of two or more storage plates by consecutively depositing layers of dielectric and conductor and making contact to the ground plates by etching an aperture through the plates to the buried plate in the substrate and connecting the... | 10/09/2008 |
| 20080237675 | Capacitor, method of increasing a capacitance area of same, and system containing same A capacitor includes a substrate (110, 210), a first electrically insulating layer (120, 220) over the substrate, and a fin (130, 231) including a semiconducting material (135) over the first electrically insulating layer. A first electricall... | 10/02/2008 |
| 20080211002 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME This semiconductor device includes: a first cylinder interlayer insulating film; a second cylinder interlayer insulating film; a cylinder hole including a first cylinder hole and a second cylinder hole communicating with the first cylinder hole; and a capacitor includin... | 09/04/2008 |
| 20080164506 | PN JUNCTION AND MOS CAPACITOR HYBRID RESURF TRANSISTOR A high voltage semiconductor device, such as a RESURF transistor, having improved properties, including reduced on state resistance. The device includes a semiconductor substrate; a source region and a drain region provided in the substrate; wherein the source region an... | 07/10/2008 |
| 20080142862 | METHOD OF FABRICATING A TRENCH CAPACITOR HAVING INCREASED CAPACITANCE The present invention pertains to a method of fabricating a trench capacitor having increased capacitance. To tackle a difficult problem of etching deeper trenches having very high aspect ratio, an epitaxial silicon growth process is employed in the fabrication of next-... | 06/19/2008 |
| 20080116498 | Method of forming a semiconductor device having a capacitor and a resistor A semiconductor device comprising the following. A structure having: a capacitor; a first resistor; and a second resistor each within at least a portion of an oxide structure and a metal-oxide semiconductor electrode not within at least a portion of the oxide structure.... | 05/22/2008 |
| 20080061341 | Memory Device Having Wide Area Phase Change Element and Small Electrode Contact Area A memory cell device of the type that includes a memory material switchable between electrical property states by application of energy, situated between first and second (“bottom” and “top”) electrodes has a top electrode including a larger body portion and a s... | 03/13/2008 |
| 20080061342 | SEMICONDUCTOR DEVICE AND METHOD FOR MAKING THE SAME A method for forming a semiconductor device is provided. The method comprises providing a substrate with recessed gates and deep trench capacitor devices therein. Protrusions of the recessed gates and upper portions of the deep trench capacitor devices are revealed. Spa... | 03/13/2008 |
| 20080048234 | Semiconductor memory device and method for fabricating same A semiconductor memory device has a first interlayer insulating film formed on a semiconductor substrate and having a capacitor opening portion provided in the film, and a capacitance element formed over the bottom and sides of the capacitor opening portion and composed... | 02/28/2008 |
| 20080029801 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME A semiconductor device includes a first insulating layer, a capacitor, an adhesive layer, and an intermediate layer. The first insulating layer may include a first insulating film. The first insulating layered structure has a first hole. The capacitor is disposed in the... | 02/07/2008 |
| 20070267673 | Adjustable on-chip sub-capacitor design One or more on-chip VNCAP or MIMCAP capacitors utilize a variable MOS capacitor to improve the uniform capacitance value of the capacitors. This permits the production of silicon semiconductor chips on which are mounted capacitors having capacitive values that are preci... | 11/22/2007 |
| 20070235788 | Poly-Insulator-Poly Capacitor and Fabrication Method for Making the Same A poly-insulator-poly (PIP) capacitor includes a first polysilicon plate; a first capacitor dielectric layer disposed on the first polysilicon plate; a second polysilicon plate stacked on the first capacitor dielectric layer, wherein the first polysilicon plate, the fir... | 10/11/2007 |
| 20070200139 | Semiconductor device, manufacturing method thereof, and display device A multi-gate structure is used and a width (d1) of a high concentration impurity region sandwiched by two channel forming regions in a channel length direction is set to be shorter than a width (d2) of low concentration impurity regions in the channel leng... | 08/30/2007 |
| 20070187737 | TERRACED FILM STACK A process and apparatus directed to forming a terraced film stack of a semiconductor device, for example, a DRAM memory device, is disclosed. The present invention addresses etch undercut resulting from materials of different etch selectivity used in the film stack, whi... | 08/16/2007 |
| 20070187738 | Stud electrode and process for making same A process of making a stud capacitor structure is disclosed. The process includes embedding the stud in a dielectric stack. In one embodiment, the process includes forming an electrically conductive seed film in a contact corridor of the dielectric stack. A storage cell... | 08/16/2007 |
| 20070138531 | Metal-insulator-metal capacitors A metal-insulator-metal (MIM) capacitor is provided. The bottom electrode of the MIM capacitor is electrically connected to a connection node. The connection node may be, for example, a contact formed in an interlayer dielectric, a polysilicon connection node, a doped p... | 06/21/2007 |
| 20070122992 | Electronic component manufacturing method and electronic component The electronic component includes a base material, a capacitor unit, and a wiring portion. The capacitor unit has a stacked structure including a first electrode portion provided on the base material, a second electrode portion including a first surface opposing the fir... | 05/31/2007 |
| 20070108492 | Semiconductor device and method for producing the same A semiconductor device including a lower electrode formed in a groove portion, a capacitor insulating film provided so as to cover the lower electrode, and an upper electrode provided so as to cover a plurality of lower electrodes with the capacitor insulating film, whe... | 05/17/2007 |
| 20070102746 | Semiconductor integrated circuit devices and methods of forming the same A semiconductor integrated circuit device includes a first interlayer insulation film having a contact therein. The contact has an upper surface and including a void therein having an open upper portion. The device further includes a plasma damage reduction unit includi... | 05/10/2007 |
| 20070102745 | CAPACITOR STRUCTURE A capacitor structure is described, including a first capacitor and a second capacitor. The first capacitor includes a first electrode, a second electrode and a first insulating layer, wherein the second electrode is disposed under the first electrode and the first insu... | 05/10/2007 |
