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Method and apparatus for making a drink hop along a bar or counter
A method for generating a drink which appears to hop from a remote spot on the bar or counter and take one or more leaps, before landing in a patron's glass.
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| Application No. | Application Title | Issue Date |
| 20120025288 | SOI Trench DRAM Structure With Backside Strap In one exemplary embodiment, a semiconductor structure including: a silicon-on-insulator substrate having of a top silicon layer overlying an insulation layer, where the insulation layer overlies a bottom silicon layer; a capacitor disposed at least partially in the ins... | 02/02/2012 |
| 20120012911 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME A semiconductor device comprises: a semiconductor substrate including a cell region and a peripheral region; an insulating film formed on the top portion of the semiconductor substrate of the cell region; a bit line contact hole including the etched insulating film to e... | 01/19/2012 |
| 20110284941 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE A semiconductor device includes: a transistor including source and drain diffusion-layers, a gate insulating film and a gate electrode; first and second plugs formed in a first interlayer-insulating film and connected to the source and drain diffusion-layers, respective... | 11/24/2011 |
| 20110233634 | Embedded DRAM Integrated Circuits with Extremely Thin Silicon-On-Insulator Pass Transistors Integrated circuits having combined memory and logic functions are provided. In one aspect, an integrated circuit is provided. The integrated circuit comprises: a substrate comprising a silicon layer over a BOX layer, wherein a select region of the silicon layer has a t... | 09/29/2011 |
| 20110215389 | DRAM CELL TRANSISTOR DEVICE AND METHOD A semiconductor integrated circuit device includes a substrate, a well structure within the substrate, a first region, a second region, and multiple isolation regions within the well structure. The device further includes a channel region within the first region, a gate... | 09/08/2011 |
| 20110204429 | DYNAMIC RANDOM ACCESS MEMORY (DRAM) CELLS AND METHODS FOR FABRICATING THE SAME A semiconductor memory cell is provided that includes a trench capacitor and an access transistor. The access transistor comprises a source region, a drain region, a gate structure overlying the trench capacitor, and an active body region that couples the drain region t... | 08/25/2011 |
| 20110193149 | SILICON-ON-INSULATOR SUBSTRATE WITH BUILT-IN SUBSTRATE JUNCTION A method of forming a SOI substrate, diodes in the SOI substrate and electronic devices in the SOI substrate and an electronic device formed using the SOI substrate. The method of forming the SOI substrate includes forming an oxide layer on a silicon first substrate; io... | 08/11/2011 |
| 20110169065 | METHOD AND STRUCTURE FOR FORMING CAPACITORS AND MEMORY DEVICES ON SEMICONDUCTOR-ON-INSULATOR (SOI) SUBSTRATES A device is provided that includes memory, logic and capacitor structures on a semiconductor-on-insulator (SOI) substrate. In one embodiment, the device includes a semiconductor-on-insulator (SOI) substrate having a memory region and a logic region. Trench capacitors ar... | 07/14/2011 |
| 20110169131 | DEEP TRENCH DECOUPLING CAPACITOR Solutions for forming a silicided deep trench decoupling capacitor are disclosed. In one aspect, a semiconductor structure includes a trench capacitor within a silicon substrate, the trench capacitor including: an outer trench extending into the silicon substrate; a die... | 07/14/2011 |
| 20110163366 | Semiconductor Component Arrangement Comprising a Trench Transistor Disclosed is a semiconductor component arrangement and a method for producing a semiconductor component arrangement. The method comprises producing a trench transistor structure with at least one trench disposed in the semiconductor body and with at least an gate electr... | 07/07/2011 |
| 20110140186 | CAPACITOR FOR SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF CAPACITOR FOR SEMICONDUCTOR DEVICE Disclosed are a capacitor for a semiconductor device and a manufacturing method thereof. The capacitor includes a second oxide layer filling a first trench in a semiconductor substrate; second and third trenches in an active region at opposing sides of the second oxide ... | 06/16/2011 |
| 20110121377 | RESERVOIR CAPACITOR OF SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME A method for fabricating a reservoir capacitor of a semiconductor device where a first peripheral circuit region and a second peripheral circuit region are defined comprises: forming a gate on an upper portion of a semiconductor substrate of the second peripheral circui... | 05/26/2011 |
| 20110101435 | BURIED BIT LINE PROCESS AND SCHEME The embodiment provides a buried bit line process and scheme. The buried bit line is disposed in a trench formed in a substrate. The buried bit line includes a diffusion region formed in a portion of the substrate adjacent the trench. A blocking layer is formed on a por... | 05/05/2011 |
| 20110001176 | SELF-ALIGNMENT INSULATION STRUCTURE An insulation structure is provided. The insulation structure includes a deep trench filled with silicon and disposed in a substrate, a first oxide layer serving as the insulation structure and disposed on the surface of the silicon in the deep trench, a first silicon l... | 01/06/2011 |
| 20100264456 | Capacitor Structure in Trench Structures of Semiconductor Devices and Semiconductor Devices Comprising Capacitor Structures of this Type and Methods for Fabricating the Same A capacitor structure in trench structures of a semiconductor device includes conductive regions made of metallic and/or semiconducting materials. The conducting regions are surrounded by a dielectric and form stacked layers in the trench structure of the semiconductor ... | 10/21/2010 |
| 20100252873 | TRENCH STRUCTURE AND METHOD OF FORMING THE TRENCH STRUCTURE Disclosed are embodiments of an improved deep trench capacitor structure and memory device that incorporates this deep trench capacitor structure. The deep trench capacitor and memory device embodiments are formed on a semiconductor-on-insulator (SOI) wafer such that th... | 10/07/2010 |
| 20100244112 | INTEGRATED CIRCUIT STRUCTURES WITH SILICON GERMANIUM FILM INCORPORATED AS LOCAL INTERCONNECT AND/OR CONTACT Disclosed are integrated circuit structures each having a silicon germanium film incorporated as a local interconnect and/or an electrical contact. These integrated circuit structures provide improved local interconnects between devices and/or increased capacitance to d... | 09/30/2010 |
| 20100230736 | High Voltage Deep Trench Capacitor A semiconductor process and apparatus provide a high voltage deep trench capacitor structure (10) that is integrated in an integrated circuit, alone or in alignment with a fringe capacitor (5). The deep trench capacitor structure is constructed from a firs... | 09/16/2010 |
| 20100230735 | Deep Trench Capacitor on Backside of a Semiconductor Substrate A pair of through substrate vias is formed through a stack including a lightly doped semiconductor and a bottom semiconductor layer in a semiconductor substrate. The top semiconductor layer includes semiconductor devices such as field effect transistors. At least one de... | 09/16/2010 |
| 20100224925 | METAL-INSULATOR-METAL STRUCTURE FOR SYSTEM-ON-CHIP TECHNOLOGY The present disclosure provides a semiconductor device that includes a semiconductor substrate, an isolation structure formed in the semiconductor substrate, a conductive layer formed over the isolation structure, and a metal-insulator-metal (MIM) capacitor formed over ... | 09/09/2010 |
| 20100213522 | METHOD FOR FORMING A SEMICONDUCTOR STRUCTURE TO REMEDY BOX UNDERCUT AND STRUCTURE FORMED THEREBY A method of forming a silicon-on-insulator (SOI) semiconductor structure in a substrate having a bulk semiconductor layer, a buried oxide (BOX) layer and an SOI layer. During the formation of a trench in the structure, the BOX layer is undercut. The method includes form... | 08/26/2010 |
| 20100193852 | EMBEDDED DRAM MEMORY CELL WITH ADDITIONAL PATTERNING LAYER FOR IMPROVED STRAP FORMATION The present invention relates to semiconductor devices, and more particularly to a structure and method for forming memory cells in a semiconductor device using a patterning layer and etch sequence. The method includes forming trenches in a layered semiconductor structu... | 08/05/2010 |
| 20100181607 | INCREASING THE SURFACE AREA OF A MEMORY CELL CAPACITOR Methods and apparatuses to increase a surface area of a memory cell capacitor are described. An opening in a second insulating layer deposited over a first insulating layer on a substrate is formed. The substrate has a fin. A first insulating layer is deposited over the... | 07/22/2010 |
| 20100155801 | Integrated circuit, 1T-1C embedded memory cell containing same, and method of manufacturing 1T-1C memory cell for embedded memory application An integrated circuit includes a semiconducting substrate (110), electrically conductive layers (120) over the semiconducting substrate, and a capacitor (130) at least partially embedded within the semiconducting substrate such that the capacitor is... | 06/24/2010 |
| 20100102373 | TRENCH MEMORY WITH SELF-ALIGNED STRAP FORMED BY SELF-LIMITING PROCESS A semiconductor structure is described. The structure includes a trench opening formed in a semiconductor substrate having a semiconductor-on-insulator (SOI) layer and a buried insulating (BOX) layer; and a filling material formed in the trench opening, the filling mate... | 04/29/2010 |
| 20100090264 | INTERCONNECT STRUCTURE FOR SEMICONDUCTOR DEVICES One embodiment relates to an integrated circuit formed on a semiconductor body having interconnect between source/drain regions of a first and second transistor. The interconnect includes a metal body arranged underneath the surface of the semiconductor body. A contact ... | 04/15/2010 |
| 20100059806 | Semiconductor device A semiconductor device is proposed in which signal delay due to compensation capacitance elements in peripheral circuit element regions is eliminated. The semiconductor device includes: a first region including memory cells; a second region 10 including a functio... | 03/11/2010 |
| 20100052026 | DEEP TRENCH CAPACITOR FOR SOI CMOS DEVICES FOR SOFT ERROR IMMUNITY A semiconductor structure is disclosed. The semiconductor structure includes an active semiconductor layer, a semiconductor device having a gate disposed on top of the active semiconductor layer, and source and drain regions and a body/channel region disposed within the... | 03/04/2010 |
| 20100044766 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE Disclosed is a semiconductor device of n-type MOSFET structure, which comprises a semiconductor substrate having a device isolation region, diffusion regions formed in the semiconductor substrate, gate electrodes formed above the semiconductor substrate, and a F-contain... | 02/25/2010 |
| 20100032742 | INTEGRATED CIRCUITS COMPRISING AN ACTIVE TRANSISTOR ELECTRICALLY CONNECTED TO A TRENCH CAPACITOR BY AN OVERLYING CONTACT AND METHODS OF MAKING A method of forming an integrated circuit comprises: providing a semiconductor topography comprising an active transistor laterally adjacent to a trench capacitor formed in a semiconductor substrate, the active transistor comprising a source junction and a drain junctio... | 02/11/2010 |
| 20100006913 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME A semiconductor device includes: a semiconductor substrate including a trench; a capacitor electrode formed in the trench; a first insulation film formed on a bottom of the trench and between the semiconductor substrate and the capacitor electrode; a second insulation f... | 01/14/2010 |
| 20090302366 | STRUCTURE AND DESIGN STRUCTURE HAVING ISOLATED BACK GATES FOR FULLY DEPLETED SOI DEVICES Methods, structure and design structure having isolated back gates for fully depleted semiconductor-on-insulator (FDSOI) devices are presented. In one embodiment, a method may include providing a FDSOI substrate having a SOI layer over a buried insulator over a first po... | 12/10/2009 |
| 20090289291 | SOI DEEP TRENCH CAPACITOR EMPLOYING A NON-CONFORMAL INNER SPACER A bottle shaped trench for an SOI capacitor is formed by a simple processing sequence. A non-conformal dielectric layer with an optional conformal dielectric diffusion barrier layer underneath is formed on sidewalls of a deep trench. Employing an isotropic etch, the non... | 11/26/2009 |
| 20090256185 | METALLIZED CONDUCTIVE STRAP SPACER FOR SOI DEEP TRENCH CAPACITOR A conductive strap spacer is formed within a buried strap cavity above an inner electrode recessed below a top surface of a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A portion of the conductive strap spacer is metallized by reacting with a ... | 10/15/2009 |
| 20090250738 | SIMULTANEOUS BURIED STRAP AND BURIED CONTACT VIA FORMATION FOR SOI DEEP TRENCH CAPACITOR A node dielectric, an inner electrode, and a buried strap cavity are formed in the deep trench in an SOI substrate. A buried layer contact cavity is formed by lithographic methods. The buried strap cavity and the buried layer contact cavity are filled simultaneously by ... | 10/08/2009 |
| 20090250787 | SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD OF THE SAME A semiconductor storage device includes: a first conductive adhesive layer selectively formed over a semiconductor substrate; an insulating film formed on the semiconductor substrate to cover the first conductive adhesive layer and having an opening exposing a central p... | 10/08/2009 |
| 20090242953 | SHALLOW TRENCH CAPACITOR COMPATIBLE WITH HIGH-K / METAL GATE Forming a shallow trench capacitor in conjunction with an FET by forming a plurality of STI trenches; for the FET, implanting a first cell well having a first polarity between a first and a second of the STI trenches; for the capacitor, implanting a second cell well hav... | 10/01/2009 |
| 20090242954 | MEMORY DEVICE AND FABRICATION THEREOF The invention is related to a memory device, including a substrate, a capacitor which is substantially C-shaped in a cross section parallel to the substrate surface and a word line coupling the capacitor. In an embodiment, the C-shaped capacitor is a deep trench capacit... | 10/01/2009 |
| 20090184356 | DEEP TRENCH CAPACITOR IN A SOI SUBSTRATE HAVING A LATERALLY PROTRUDING BURIED STRAP A deep trench is formed to a depth midway into a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A top semiconductor layer is laterally recessed by an isotropic etch that is selective to the buried insulator layer. The deep trench is then etched ... | 07/23/2009 |
| 20090173980 | PROVIDING ISOLATION FOR WORDLINE PASSING OVER DEEP TRENCH CAPACITOR A memory cell has an access transistor and a capacitor with an electrode disposed within a deep trench. STI oxide covers at least a portion of the electrode, and a liner covers a remaining portion of the electrode. The liner may be a layer of nitride over a layer of oxi... | 07/09/2009 |
