...that on Dec. 15, 1836, the Patent Office was completely destroyed by fire? Lost were some 7,000 models, 9,000 drawings, and 230 books plus all records of patent applications and grants.
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| Application No. | Application Title | Issue Date |
| 20110170343 | DRAM MEMORY CELL HAVING A VERTICAL BIPOLAR INJECTOR The invention relates to a memory cell having an FET transistor with a source, a drain and a floating body between the source and the drain, and an injector that can be controlled to inject a charge into the floating body of the FET transistor. The injector includes a b... | 07/14/2011 |
| 20100019291 | JFET Devices with PIN Gate Stacks and Methods of Making the Same Devices and methods for providing JFET transistors with improved operating characteristics are provided. Specifically, one or more embodiments of the present invention relate to JFET transistors with a higher diode turn-on voltage. For example, one or more embodiments i... | 01/28/2010 |
| 20090245543 | AMPLIFYING ELEMENT AND MANUFACTURING METHOD THEREOF An amplifier integrated circuit element or J-FET is used for impedance conversion and amplification of ECM. The amplifier integrated circuit element has advantages of allowing an appropriate gain to be set by adjusting a circuit constant, and of producing a higher gain ... | 10/01/2009 |
| 20090057728 | DYNAMIC RANDOM ACCESS MEMORY HAVING JUNCTION FIELD EFFECT TRANSISTOR CELL ACCESS DEVICE A dynamic random access memory (DRAM) device can include a plurality of memory cells. Each memory cell can include a charge storing structure and an access device comprising an enhancement mode junction field effect transistor (JFET). The DRAM device can further include... | 03/05/2009 |
| 20080308849 | SEMICONDUCTOR APPARATUS AND COMPLIMENTARY MIS LOGIC CIRCUIT A configuration is adopted comprising an NchMOS transistor 1 equipped with an insulating isolation layer 4 providing insulation and isolation using an SOI structure, and a capacitor formed using an insulating film, with a silicon substrate B being made thi... | 12/18/2008 |
| 20080237657 | Signaling circuit and method for integrated circuit devices and systems An integrated circuit device can include at least one bipolar junction transistor (BJT) having a first base electrode comprising a semiconductor material doped to a first conductivity type formed on and in contact with a surface of the semiconductor substrate, and separ... | 10/02/2008 |
| 20080079035 | Symmetric blocking transient voltage suppressor (TVS) using bipolar transistor base snatch A symmetrical blocking transient voltage suppressing (TVS) circuit for suppressing a transient voltage includes an NPN transistor having a base electrically connected to a common source of two transistors whereby the base is tied to a terminal of a low potential in eith... | 04/03/2008 |
| 20080067559 | Heterogeneous integration of low noise amplifiers with power amplifiers or switches A transistor heterogeneously integrating a power amplifier or switch with a low-noise amplifier having a substrate wafer selected from a group consisting of Gallium Arsenide (GaAs), Indium Phosphate (InP) and Gallium Antimonide (GaSb), the substrate wafer having a first... | 03/20/2008 |
| 20080017895 | VERTICAL-TYPE, INTEGRATED BIPOLAR DEVICE AND MANUFACTURING PROCESS THEREOF A bipolar device is integrated in an active layer, wherein delimitation trenches surround respective active areas housing bipolar transistors of complementary types. Each active area accommodates a buried layer; a well region extending on top of the buried layer; a top ... | 01/24/2008 |
| 20080012051 | Dynamic Random Access Memory with an Amplified Capacitor A memory cell and methods of making and operating the same are provided. In one aspect, a method of forming a memory cell is provided that includes forming a MOS transistor that has a gate, a source region and a drain region. A bipolar transistor is formed that has a co... | 01/17/2008 |
| 20070290237 | INSULATED GATE BIPOLAR TRANSISTOR AND METHOD FOR MANUFACTURING SAME An insulated gate bipolar transistor has a p-type emitter layer; an n-type buffer layer provided on the p-type emitter layer; an n-type base layer provided on the n-type buffer layer and having a higher resistivity than the n-type buffer layer; a p-type base layer provi... | 12/20/2007 |
| 20070254446 | Self-aligned biopolar junction transistors A plurality of bipolar transistors are formed by forming a common conduction region, a plurality of control regions extending each in an own active areas on the common conduction region, a plurality of silicide protection strips, and at least one control contact region.... | 11/01/2007 |
| 20070246750 | Control of body potential of partially-depleted field-effect transistors A partially-depleted silicon-on-insulator (SOI) field-effect transistor (FET) with a reduced off-current is described, as well as methods for manufacturing. This may be accomplished by providing an SOI FET having a lower body potential than in previous SOI FETs. To lowe... | 10/25/2007 |
| 20070200150 | Voltage-controlled semiconductor device SiC-IGBTs, which have an inversion-type channel with high channel resistance and have high on-voltage due to an influence from the surface state of the interface between a gate insulating film and a base layer, are required to decrease the on-voltage. An embedded collec... | 08/30/2007 |
| 20070122963 | Latch-up prevention in semiconductor circuits This invention discloses a semiconductor device with latch-up prevention mechanisms. According to one embodiment, it comprises a first doping region, wherein one or more semiconductor devices are disposed therein and coupling to a first supply voltage, a second doping r... | 05/31/2007 |
| 20070114577 | SEMICONDUCTOR DEVICE One of the aspects of the present invention is to provide a semiconductor device, which includes a semiconductor substrate, a surface electrode on the semiconductor substrate, and a gate wiring on the semiconductor substrate, the gate wiring being spaced from the surfac... | 05/24/2007 |
| 20070108479 | RESISTANCE ELEMENT HAVING REDUCED AREA A semiconductor device having reduced area occupied by the semiconductor elements that constitute the semiconductor device, and its manufacturing method. Insulating film 12 is formed on substrate 10. First resistance element 18b is formed on insulat... | 05/17/2007 |
| 20070069252 | Insulated gate semiconductor device having a clamping element to clamp gate-emitter voltage and method of manufacturing thereof The gate of an IGBT is connected to a gate terminal. One end of a clamping element is connected to an anode terminal. A voltage higher than a clamping voltage is applied between the gate and the emitter, to thereby test the dielectric breakdown voltage of a gate insulat... | 03/29/2007 |
| 20070034909 | Nanometer-scale semiconductor devices and method of making A semiconductor device including a substrate having a dopant of a first polarity, a first semiconducting structure including a dopant of a second polarity disposed over the substrate, and having substantially planar top and side surfaces. The semiconductor device includ... | 02/15/2007 |
| 20060255376 | Integrated circuit and method for manufacturing an integrated circuit An integrated circuit is disclosed, the integrated circuit comprises: a vertically integrated bipolar transistor; and at least one emitter resistor, which is connected conductively to an emitter semiconductor region of the vertically integrated bipolar transistor. A col... | 11/16/2006 |
| 20060258077 | Formation of deep trench airgaps and related applications A method for forming deep trench or via airgaps in a semiconductor substrate is disclosed comprising the steps of patterning a hole in the substrate, partly fill said hole with a sacrificial material (e.g. poly-Si), depositing spacers on the sidewalls of the unfilled pa... | 11/16/2006 |
| 20060151815 | Weighted gradient method and system for diagnosing disease A method for detecting and diagnosing disease states in a body part is described. The method starts with a preparatory step of modeling the body part as a grid of many finite elements, then calculating an electrical property between two finite elements at which current ... | 07/13/2006 |
| 20060076583 | Semiconductor device and manufacturing method thereof A semiconductor device has a MOS gate side surface structure, including a gate electrode filling a trench formed in a semiconductor substrate with an insulator film between the trench and the gate electrode, a gate insulator film covering the surface of the gate electro... | 04/13/2006 |
| 20060071247 | Reliable high-voltage junction field effect transistor and method of manufacture therefor The present invention provides a high-voltage junction field effect transistor (JFET), a method of manufacture and an integrated circuit including the same. One embodiment of the high-voltage junction field effect transistor (JFET) (300) includes a well region (<... | 04/06/2006 |
| 20060049434 | Semiconductor device and manufacturing method thereof A semiconductor device and method of manufacturing the same includes an n−-single crystal silicon substrate, with an oxide film selectively formed thereon. On the oxide film, gate polysilicon is formed. The surface of the gate polysilicon is covered with a ... | 03/09/2006 |
| 20060038206 | Semiconductor device and manufacturing method thereof A thin semiconductor wafer, on which a top surface structure and a bottom surface structure that form a semiconductor chip are formed, is affixed to a supporting substrate by a double-sided adhesive tape. Then, on the thin semiconductor wafer, a trench to become a scrib... | 02/23/2006 |
| 20050272214 | Electrophoretic assembly of electrochemical devices Methods are provided for making bipolar electrochemical devices, such as batteries, using electrophoresis. A bipolar device is assembled by applying a field that creates a physical separation between two active electrode materials, without requiring insertion of a discr... | 12/08/2005 |