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| Application No. | Application Title | Issue Date |
| 20110316055 | SUBSTRATE PROVIDED WITH A SEMI-CONDUCTING AREA ASSOCIATED WITH TWO COUNTER-ELECTRODES AND DEVICE COMPRISING ONE SUCH SUBSTRATE A support substrate comprises first and second counter-electrodes arranged in the same plane at the level of a surface of the support substrate. An electrically insulating area separates the first and second counter-electrodes. A semi-conducting area with first and seco... | 12/29/2011 |
| 20110254059 | STRUCTURE AND METHOD FOR MANUFACTURING ASYMMETRIC DEVICES A plurality of gate structures are formed on a substrate. Each of the gate structures includes a first gate electrode and source and drain regions. The first gate electrode is removed from each of the gate structures. A first photoresist is applied to block gate structu... | 10/20/2011 |
| 20110228575 | JUNCTION FIELD EFFECT TRANSISTOR, INTEGRATED CIRCUIT FOR SWITCHING POWER SUPPLY, AND SWITCHING POWER SUPPLY A switching power supply has a start-up circuit that includes a field effect transistor (JFET), which has a gate region (a p-type well region) formed in a surface layer of a p-type substrate and a drift region (a first n-type well region). A plurality of source regions ... | 09/22/2011 |
| 20110227135 | SCHOTTKY DIODES Improved Schottky diodes with reduced leakage current and improved breakdown voltage are provided by building a JFET with its current path of a first conductivity type serially located between a first terminal comprising a Schottky contact and a second terminal. The cur... | 09/22/2011 |
| 20110220973 | JUNCTION-FIELD-EFFECT-TRANSISTOR DEVICES AND METHODS OF MANUFACTURING THE SAME A junction-field-effect-transistor (JFET) device includes a substrate of a first-type impurity, a first well region of a second-type impurity in the substrate, a pair of second well regions of the first-type impurity separated from each other in the first well region, a... | 09/15/2011 |
| 20110210379 | FIN-JFET Methods, devices, and systems integrating Fin-JFETs and Fin-MOSFETs are provided. One method embodiment includes forming at least on Fin-MOSFET on a substrate and forming at least on Fin-JFET on the substrate.... | 09/01/2011 |
| 20110193142 | Structure and Method for Post Oxidation Silicon Trench Bottom Shaping A method of fabricating an LFCC device includes forming a first trench in a substrate that extends vertically from an upper surface to a depth within the substrate, the first trench having first sidewalls, a first bottom, and a pattern formed on the first sidewalls near... | 08/11/2011 |
| 20110147808 | ASYMMETRIC JUNCTION FIELD EFFECT TRANSISTOR A junction field effect transistor (JFET) in a semiconductor substrate includes a source region, a drain region, a channel region, an upper gate region, and a lower gate region. The lower gate region is electrically connected to the upper gate region. The upper and lowe... | 06/23/2011 |
| 20110101424 | JUNCTION FIELD EFFECT TRANSISTOR A junction field effect transistor having a drain and a source, each defined by regions of a first type of semiconductor interconnected by a channel, and in which a dopant profile at a side of the drain facing the channel is modified so as to provide a region of reduced... | 05/05/2011 |
| 20110079824 | ALTERNATE 4-TERMINAL JFET GEOMETRY TO REDUCE GATE TO SOURCE CAPACITANCE A 4-Terminal JFET includes a substrate having a first conduction type and an upper layer having a second, opposite, conduction type over the substrate. A gate and a source are embedded in the upper layer. A gate pad is electrically connected to the gate. A region, which... | 04/07/2011 |
| 20110068377 | HIGH VOLTAGE JUNCTION FIELD EFFECT TRANSISTOR WITH SPIRAL FIELD PLATE In one embodiment, a junction field effect transistor having a substrate, wherein formed on the substrate is a graded n-doped region having a high doping concentration in an inner region and a low doping concentration in an outer region, with a p-doped buried region adj... | 03/24/2011 |
| 20110042726 | High-voltage transistor device with integrated resistor A high-voltage device structure comprises a resistor coupled to a tap transistor that includes a JFET in a configuration wherein a voltage provided at a terminal of the JFET is substantially proportional to an external voltage when the external voltage is less than a pi... | 02/24/2011 |
| 20100295101 | INTEGRATED JFET AND SCHOTTKY DIODE The present invention discloses an integrated junction field effect transistor (JFET) and Schottky diode, comprising a depletion mode JFET which includes a source, a drain and a gate, wherein the drain is not provided with an ohmic contact such that it forms a Schottky ... | 11/25/2010 |
| 20100289067 | High Voltage III-Nitride Semiconductor Devices A III-N device is described has a buffer layer, a first III-N material layer on the buffer layer, a second III-N material layer on the first III-N material layer on an opposite side from the buffer layer and a dispersion blocking layer between the buffer layer and the c... | 11/18/2010 |
| 20100283061 | HIGH TEMPERATURE GATE DRIVERS FOR WIDE BANDGAP SEMICONDUCTOR POWER JFETS AND INTEGRATED CIRCUITS INCLUDING THE SAME Gate drivers for wide bandgap (e.g., >2 eV) semiconductor junction field effect transistors (JFETs) capable of operating in high ambient temperature environments are described. The wide bandgap (WBG) semiconductor devices include silicon carbide (SiC) and gallium nit... | 11/11/2010 |
| 20100271133 | Electronic Circuits including a MOSFET and a Dual-Gate JFET Electronic circuits and methods are provided for various applications including signal amplification. An exemplary electronic circuit comprises a MOSFET and a dual-gate JFET in a cascode configuration. The dual-gate JFET includes top and bottom gates disposed above and ... | 10/28/2010 |
| 20100252867 | MFMS-FET, Ferroelectric Memory Device, And Methods Of Manufacturing The Same Disclosed herein are a metal-ferroelectric-metal-substrate (MFMS) field-effect transistor (FET), an MFMS-ferroelectric memory device, and method of manufacturing the same. The MFMS-FET and the ferroelectric memory device in accordance with the present invention include:... | 10/07/2010 |
| 20100207174 | SEMINCONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF The invention provides a method for forming a semiconductor structure. A plurality of first type well regions is formed in the first type substrate. A plurality of second type well regions and a plurality of second type bar doped regions are formed in the first type sub... | 08/19/2010 |
| 20100155789 | LOW NOISE JFET A low noise (1/f) junction field effect transistor (JFET) is disclosed, wherein multiple implants push a conduction path of the transistor away from the surface of a layer upon which the transistor is formed. In this manner, current flow in the conduction path is less l... | 06/24/2010 |
| 20100148718 | SEMICONDUCTOR ELEMENT AND ELECTRICAL APPARATUS A semiconductor element (20) of the present invention includes a plurality of field effect transistors (90) and a schottky electrode (9a), and the schottky electrode (9a) is formed along an outer periphery of a region where the ... | 06/17/2010 |
| 20100148225 | LOW POWER MEMORY DEVICE WITH JFET DEVICE STRUCTURES There is provided a low power memory device with JFET device structures. Specifically, a low power memory device is provided that includes a plurality memory cells having a memory element and a JFET access device electrically coupled to the memory element. The memory ce... | 06/17/2010 |
| 20100123171 | Multi-level Lateral Floating Coupled Capacitor Transistor Structures A semiconductor device includes a source region, a drain region, a gate region, and a drift region. The drift region further includes an active drift region and inactive floating charge control (FCC) regions. The active drift region conducts current between the source r... | 05/20/2010 |
| 20100090260 | Integrated circuit layout pattern for cross-coupled circuits A circuit 32 is provided comprising a first diffusion region 34 and a parallel second diffusion region 36. A sequence of N gate layers 40, 42, 46 is provided with a first and an Nth of these gate layers covering different respective ones of t... | 04/15/2010 |
| 20100065894 | Semiconductor Device Having a Field Effect Source/Drain Region A semiconductor device includes an active region defined in a semiconductor substrate, and gate electrodes crossing over the active region. Source/drain regions are defined in the active region on two sides of the gate electrode. At least one of the source/drain regions... | 03/18/2010 |
| 20100032729 | INTEGRATION OF HIGH VOLTAGE JFET IN LINEAR BIPOLAR CMOS PROCESS A dual channel JFET which can be integrated in an IC without adding process steps is disclosed. Pinch-off voltage is determined by lateral width of a first, vertical, channel near the source contact. Maximum drain voltage is determined by drain to gate separation and le... | 02/11/2010 |
| 20090282382 | SYSTEM AND METHOD FOR ROUTING CONNECTIONS WITH IMPROVED INTERCONNECT THICKNESS A method for modeling a circuit includes generating a circuit model based on a netlist that defines a plurality of connections between a plurality of circuit elements. The circuit model includes a model of one or more of the circuit elements. The method further includes... | 11/12/2009 |
| 20090278177 | SEMICONDUCTOR DEVICES WITH NON-PUNCH-THROUGH SEMICONDUCTOR CHANNELS HAVING ENHANCED CONDUCTION AND METHODS OF MAKING Semiconductor devices are described wherein current flow in the device is confined between the rectifying junctions (e.g., p-n junctions or metal-semiconductor junctions). The device provides non-punch-through behavior and enhanced current conduction capability. The dev... | 11/12/2009 |
| 20090224290 | Two-way Halo Implant A system and method for ion implantation during semiconductor fabrication. An integrated circuit may be designed with proximately located one-directional transistor gates. A two-way halo ion implantation is performed perpendicularly to the transistor gates in order to e... | 09/10/2009 |
| 20090039398 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME An n type impurity region is continuously formed on the bottom portion of a channel region below a source region, a gate region and a drain region. The n type impurity region has an impurity concentration higher than the channel region and a back gate region, and is les... | 02/12/2009 |
| 20090026506 | SEMICONDUCTOR DEVICE In the semiconductor device, a gate region is formed in a mesh pattern having first polygonal shapes and second polygonal shapes the area of which is smaller than that of the first polygonal shapes, and drain regions and source regions are disposed within the first poly... | 01/29/2009 |
| 20080285322 | Junction field effect dynamic random access memory cell and content addressable memory cell A semiconductor memory device including a dynamic random access memory (DRAM) cell and a ternary content addressable memory (TCAM) cell is disclosed. The DRAM cell may include a data storing portion and a data read portion. The data storing portion and data read portion... | 11/20/2008 |
| 20080272408 | ACTIVE AREA JUNCTION ISOLATION STRUCTURE AND JUNCTION ISOLATED TRANSISTORS INCLUDING IGFET, JFET AND MOS TRANSISTORS AND METHOD FOR MAKING Integrated active area isolation structure for transistor to replace larger and more expensive Shallow Trench Isolation or field oxide to isolate transistors. Multiple well implant is formed with PN junctions between wells and with surface contacts to substrate and well... | 11/06/2008 |
| 20080230812 | Isolated junction field-effect transistor Various integrated circuit devices, in particular a junction field-effect transistor (JFET), are formed inside an isolation structure which includes a floor isolation region and a trench extending from the surface of the substrate to the floor isolation region. The tren... | 09/25/2008 |
| 20080099798 | Methods and devices for amplifying a signal A junction field effect transistor (JFET) device is disclosed for amplifying an input signal. The JFET device includes a first gate region and a substrate/well/bulk region that may form a second gate region. The JFET device also includes a first source/drain region and ... | 05/01/2008 |
| 20080073675 | Transistor with start-up control element A transistor having a start-up control element is provided. The transistor includes an N-type depletion mode transistor and an N-type enhancement mode transistor. The N-type depletion mode transistor includes a drain for electrically connecting to an external power supp... | 03/27/2008 |
| 20080074908 | Depletion mode transistor as a start-up control element A depletion mode transistor serving as a start-up control element is provided. The depletion mode transistor includes a first depletion mode junction transistor and a second depletion mode transistor. The first depletion mode junction transistor includes a source and a ... | 03/27/2008 |
| 20060255373 | Semiconductor structure comprising a highly doped conductive channel region and method for producing a semiconductor structure The invention relates to a semiconductor structure for controlling a current (I), comprising a first n-conductive semiconductor region (2), a current path that runs within the first semiconductor region (2) and a channel region (22). The channel reg... | 11/16/2006 |
| 20060231870 | CMOS image sensor and method of fabricating the same A CMOS image sensor and a method of fabricating the same are provided. The image sensor includes a blocking layer protecting a photodiode at a diode region. The blocking layer is formed to cover a top of the diode region and extended to an active region so as to cover a... | 10/19/2006 |
| 20060071247 | Reliable high-voltage junction field effect transistor and method of manufacture therefor The present invention provides a high-voltage junction field effect transistor (JFET), a method of manufacture and an integrated circuit including the same. One embodiment of the high-voltage junction field effect transistor (JFET) (300) includes a well region (<... | 04/06/2006 |
| 20060022227 | Novel buffer (seed) layer in a high performance magnetic tunneling junction MRAM An MTJ (magnetic tunneling junction) device particularly suitable for use as an MRAM (magnetic random access memory) or a tunneling magnetoresistive (TMR) read sensor, is formed on a seed layer which allows the tunneling barrier layer to be ultra-thin, smooth, and to ha... | 02/02/2006 |
