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| Application No. | Application Title | Issue Date |
| 20120104361 | TRANSISTOR USING SOURCE ELECTRODE AND DRAIN ELECTRODE HAVING POINTED PORTIONS A transistor includes a substrate, a source electrode, a drain electrode and a nanowire-layer. The source electrode, the drain electrode and the nanowires-layer are formed on the substrate. The source electrode includes a plurality of first pointed portions, and the dra... | 05/03/2012 |
| 20120068158 | INFRARED LIGHT DETECTOR Provided is an infrared light detector 100 with a plurality of first electronic regions 10 which are electrically independent from each other and arranged in a specific direction, formed by dividing a single first electronic region. An outer electron syste... | 03/22/2012 |
| 20120038409 | Nanotechnology An apparatus including a first electrode; a second electrode; a nano-scale channel between the first electrode and the second electrode wherein the nano-scale channel has a first state in which an electrical impedance of the nano-scale channel is relatively high and a s... | 02/16/2012 |
| 20120032149 | Vertical Stacking of Carbon Nanotube Arrays for Current Enhancement and Control Transistor devices having vertically stacked carbon nanotube channels and techniques for the fabrication thereof are provided. In one aspect, a transistor device is provided. The transistor device includes a substrate; a bottom gate embedded in the substrate with a top ... | 02/09/2012 |
| 20120025170 | P-TYPE SEMICONDUCTOR DEVICES A semiconductor device comprises an active layer above a first confinement layer. The active layer comprises a layer of α-Sn less than 20 nm thick. The first confinement layer is formed of material with a wider band gap than α-Sn, wherein the band gap offset between Î... | 02/02/2012 |
| 20120025169 | NANOSTRUCTURE ARRAY TRANSISTOR Transistors and methods for forming transistors from groups of nanostructures are disclosed herein. The transistor may be formed from an array of nanostructures that are grown vertically on a substrate. The nanostructures may have lower, middle and upper segments that m... | 02/02/2012 |
| 20120018704 | UNIAXIAL TENSILE STRAIN IN SEMICONDUCTOR DEVICES A semiconductor device structure comprises an active layer and a buffer layer. The active layer is a quantum well structure. There is a lattice mismatch between the buffer layer and the active layer which places the active layer under biaxial compressive strain. Uniaxia... | 01/26/2012 |
| 20120007052 | Apparatus, System, and Method for Dual-Channel Nanowire FET Device An apparatus, system, and method for dual-channel FET devices is presented. In some embodiments, the nanowire FET device may include a first transistor on a substrate, where the first transistor includes a first group of nanowires made of silicon. The nanowire FET devic... | 01/12/2012 |
| 20120007051 | Process for Forming a Surrounding Gate for a Nanowire Using a Sacrificial Patternable Dielectric Techniques for defining a damascene gate in nanowire FET devices are provided. In one aspect, a method of fabricating a FET device is provided including the following steps. A SOI wafer is provided having a SOI layer over a BOX. Nanowires and pads are patterned in the S... | 01/12/2012 |
| 20110316565 | SCHOTTKY JUNCTION SI NANOWIRE FIELD-EFFECT BIO-SENSOR/MOLECULE DETECTOR A Schottky junction silicon nanowire field-effect biosensor/molecule detector with a nanowire thickness of 10 nanometer or less and an aligned source/drain workfunction for increased sensitivity. The nanowire channel is coated with a surface treatment to which a molecul... | 12/29/2011 |
| 20110315953 | METHOD OF FORMING COMPOUND SEMICONDUCTOR A method of forming a semiconductor is provided and includes patterning a pad and a nanowire onto a wafer, the nanowire being substantially perpendicular with a pad sidewall and substantially parallel with a wafer surface and epitaxially growing on an outer surface of t... | 12/29/2011 |
| 20110315960 | TUNNEL FIELD EFFECT TRANSISTOR AND METHOD OF MANUFACTURING SAME A TFET includes a source region (110, 210), a drain region (120, 220), a channel region (130, 230) between the source region and the drain region, and a gate region (140, 240) adjacent to the channel region. The source region contains a first... | 12/29/2011 |
| 20110309332 | EPITAXIAL SOURCE/DRAIN CONTACTS SELF-ALIGNED TO GATES FOR DEPOSITED FET CHANNELS A method of forming a self-aligned device is provided and includes depositing carbon nanotubes (CNTs) onto a crystalline dielectric substrate, isolating a portion of the crystalline dielectric substrate encompassing a location of the CNTs, forming gate dielectric and ga... | 12/22/2011 |
| 20110309333 | SEMICONDUCTOR DEVICES FABRICATED BY DOPED MATERIAL LAYER AS DOPANT SOURCE A method of forming a semiconductor device is provided, in which the dopant for the source and drain regions is introduced from a doped dielectric layer. In one example, a gate structure is formed on a semiconductor layer of an SOI substrate, in which the thickness of t... | 12/22/2011 |
| 20110309334 | Graphene/Nanostructure FET with Self-Aligned Contact and Gate A method for forming a field effect transistor (FET) includes depositing a channel material on a substrate, the channel material comprising one of graphene or a nanostructure; forming a gate over a first portion of the channel material; forming spacers adjacent to the g... | 12/22/2011 |
| 20110297916 | N-and P-Channel Field-Effect Transistors with Single Quantum Well for Complementary Circuits A complementary metal oxide semiconductor (CMOS) device in which a single InxGa1-xSb quantum well serves as both an n-channel and a p-channel in the same device and a method for making the same. The InxGa1-xSb layer is part of... | 12/08/2011 |
| 20110278542 | TFET with Nanowire Source A tunnel field effect transistor (TFET) includes a source region, the source region comprising a first portion of a nanowire; a channel region, the channel region comprising a second portion of the nanowire; a drain region, the drain region comprising a portion of a sil... | 11/17/2011 |
| 20110278544 | GENERATION OF MULTIPLE DIAMETER NANOWIRE FIELD EFFECT TRANSISTORS A method of modifying a wafer having a semiconductor disposed on an insulator is provided and includes forming pairs of semiconductor pads connected via respective nanowire channels at each of first and second regions with different initial semiconductor thicknesses and... | 11/17/2011 |
| 20110278543 | GENERATION OF MUTIPLE DIAMETER NANOWIRE FIELD EFFECT TRANSISTORS A method of modifying a wafer having semiconductor disposed on an insulator is provided and includes establishing first and second regions of the wafer with different initial semiconductor thicknesses, forming pairs of semiconductor pads connected via respective nanowir... | 11/17/2011 |
| 20110272673 | DIRECTIONALLY ETCHED NANOWIRE FIELD EFFECT TRANSISTORS A method for forming a nanowire field effect transistor (FET) device includes depositing a first semiconductor layer on a substrate wherein a surface of the semiconductor layer is parallel to {110} crystalline planes of the semiconductor layer, epitaxailly depositing a ... | 11/10/2011 |
| 20110253981 | METHOD OF MANUFACTURING A VERTICAL TFET The present disclosure provides a method for manufacturing at least one nanowire Tunnel Field Effect Transistor (TFET) semiconductor device. The method comprises providing a stack comprising a layer of channel material with on top thereof a layer of sacrificial material... | 10/20/2011 |
| 20110253980 | Source/Drain Technology for the Carbon Nano-tube/Graphene CMOS with a Single Self-Aligned Metal Silicide Process Electronic devices having carbon-based materials and techniques for making contact to carbon-based materials in electronic devices are provided. In one aspect, a device is provided having a carbon-based material; and at least one electrical contact to the carbon-based m... | 10/20/2011 |
| 20110253982 | VERTICAL GROUP III-V NANOWIRES ON SI, HETEROSTRUCTURES, FLEXIBLE ARRAYS AND FABRICATION Embodiments of the invention provide a method for direct heteroepitaxial growth of vertical III-V semiconductor nanowires on a silicon substrate. The silicon substrate is etched to substantially completely remove native oxide. It is promptly placed in a reaction chamber... | 10/20/2011 |
| 20110233522 | p-FET with a Strained Nanowire Channel and Embedded SiGe Source and Drain Stressors Techniques for embedding silicon germanium (e-SiGe) source and drain stressors in nanoscale channel-based field effect transistors (FETs) are provided. In one aspect, a method of fabricating a FET includes the following steps. A doped substrate having a dielectric there... | 09/29/2011 |
| 20110233523 | SINGLE ELECTRON TRANSISTOR A single electron transistor includes source/drain layers disposed apart on a substrate, at least one nanowire channel connecting the source/drain layers, a plurality of oxide channel areas in the nanowire channel, the oxide channel areas insulating at least one portion... | 09/29/2011 |
| 20110233521 | SEMICONDUCTOR WITH CONTOURED STRUCTURE The present disclosure relates to a semiconductor device that has a first semiconductor structure that is grown to form a non-planar growth surface. The non-planar growth surface is formed from multiple facets and provides a defined contour. The defined contour may incl... | 09/29/2011 |
| 20110227043 | GRAPHENE SENSOR A method for forming a sensor includes forming a channel in substrate, forming a sacrificial layer in the channel, forming a sensor having a first dielectric layer disposed on the substrate, a graphene layer disposed on the first dielectric layer, and a second dielectri... | 09/22/2011 |
| 20110220875 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME A method for manufacturing a semiconductor device comprises: growing a carbon nano tube on a semiconductor substrate; forming an insulating film in the inside and the outside of the carbon nano tube; and forming a graphene on the surface of the insulating film, thereby ... | 09/15/2011 |
| 20110215298 | ULTRAFAST AND ULTRASENSITIVE NOVEL PHOTODETECTORS A photodetector is provided that includes a FET structure with a channel structure having one or more nanowire structures. Noble metal nanoparticles are positioned on the channel structure so as to produce a functionalized channel structure. The functionalized channel s... | 09/08/2011 |
| 20110204331 | CHARGE STORAGE NANOSTRUCTURE The present invention relates to a nanostructured device for charge storage. In particular the invention relates to a charge storage device that can be used for memory applications. According to the invention the device comprise a first nanowire with a first wrap gate a... | 08/25/2011 |
| 20110204332 | Semiconductor device and method of manufacturing the same A semiconductor device according to example embodiments may include a channel including a nanowire and a charge storage layer including nanoparticles. A twin gate structure including a first gate and a second gate may be formed on the charge storage layer. The semicondu... | 08/25/2011 |
| 20110180846 | Method for Forming Antimony-Based FETs Monolithically An integrated circuit structure includes a substrate and a first and a second plurality of III-V semiconductor layers. The first plurality of III-V semiconductor layers includes a first bottom barrier over the substrate; a first channel layer over the first bottom barri... | 07/28/2011 |
| 20110168980 | Nanofiber composite, method of manufacturing the same, and field effect transistor including the same A nanofiber composite including a nanofiber formed of a hydrophobic polymer, a nanowire formed of a conductive or semiconductive organic material that is oriented in the nanofiber in the longitudinal direction of the nanofiber, and an ionic active material.... | 07/14/2011 |
| 20110163297 | Core-Shell-Shell Nanowire Transistor A fabrication method is provided for a core-shell-shell (CSS) nanowire transistor (NWT). The method provides a cylindrical CSS nanostructure with a semiconductor core, an insulator shell, and a conductive shell. The CSS nanostructure has a lower hemicylinder overlying a... | 07/07/2011 |
| 20110163296 | CNT-BASED SENSORS: DEVICES, PROCESSES AND USES THEREOF Disclosed herein are methods of preparing and using doped MWNT electrodes, sensors and field-effect transistors. Devices incorporating doped MWNT electrodes, sensors and field-effect transistors are also disclosed.... | 07/07/2011 |
| 20110156004 | Multi-gate III-V quantum well structures Methods of forming microelectronic structures are described. Embodiments of those methods include forming a III-V tri-gate fin on a substrate, forming a cladding material around the III-V tri-gate fin, and forming a hi k gate dielectric around the cladding material.... | 06/30/2011 |
| 20110156005 | Germanium-based quantum well devices A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above a... | 06/30/2011 |
| 20110156006 | Forming A Non-Planar Transistor Having A Quantum Well Channel In one embodiment, the present invention includes an apparatus having a substrate, a buried oxide layer formed on the substrate, a silicon on insulator (SOI) core formed on the buried oxide layer, a compressive strained quantum well (QW) layer wrapped around the SOI cor... | 06/30/2011 |
| 20110147697 | Isolation for nanowire devices The present disclosure relates to the field of fabricating microelectronic devices. In at least one embodiment, the present disclosure relates to forming an isolated nanowire, wherein isolation structure adjacent the nanowire provides a substantially level surface for t... | 06/23/2011 |
| 20110147708 | INCREASING CARRIER INJECTION VELOCITY FOR INTEGRATED CIRCUIT DEVICES Embodiments of the present disclosure describe structures and techniques to increase carrier injection velocity for integrated circuit devices. An integrated circuit device includes a semiconductor substrate, a first barrier film coupled with the semiconductor substrate... | 06/23/2011 |
